Abstract
Modern computing systems consist of many processing cores, where fast and reliable communication between these cores is essential for high performance. Networks-on-Chip (NoCs) are an on-chip communication paradigm inspired by packet-switched computer networks, proposed to enable efficient and dependable communication among on-chip components. However, NoCs are vulnerable to various security threats, including spoofing, side-channel attacks, and eavesdropping. Among these, Denial-of-Service (DoS) attacks are particularly concerning due to their potential to significantly degrade system performance. Although some hardware-level modifications can be addressed during design time, no universal solution currently exists. Detecting attacks within the NoC is vital to prevent the disruption of potentially critical functionality.This thesis explores the progress and challenges in Network-on-Chip (NoC) architectures and proposes the use of third-generation Artificial Spiking Neural Networks (SNNs) for run-time DoS attack detection. SNNs are event-driven neural models that process information via discrete spikes, offering a closer resemblance to biological neural activity and reduced resource demands compared to traditional neural networks.
A Multimedia System (MMS) is used as the testbed, along with a custom suite of DoS attacks designed to generate training data and evaluate detection accuracy. Two detection strategies are introduced: the fine-grained approach, which closely monitors a single router, and the coarse-grained approach, which observes the perimeter activity of a group of routers.
Experimental results demonstrate high detection accuracy with low latency. A full-coverage attack can be identified using the fine-grained method in 427 clock cycles with just 11 neurons, while the coarse-grained method requires 540cycles and 19 neurons. Both approaches maintain a low neuron count, emphasising their suitability for hardware implementation. An FPGA-based implementation of the fine-grained module confirms its practicality, consuming approximately 76 mW of power and operating in parallel with existing systems without impacting data throughput.
Thesis embargoed until 30 June 2027
| Date of Award | Jun 2025 |
|---|---|
| Original language | English |
| Sponsors | Department for the Economy |
| Supervisor | Jim Harkin (Supervisor) & Liam Mc Daid (Supervisor) |
Keywords
- FPGA
- neuromorphics
- machine learning
- security
- SoCs