AbstractHardware has become more prone to faults, due to wear-out and faults caused during the manufacturing process. The reliability of hardware is becoming more dependent on the ability to continually adapt to faults and current fault tolerant approaches are susceptible to faults. A computational model of biological self-repair in the brain, derived from observing the distributed role of astrocytes (a glial cell found in the mammalian brain), has captured self-repair within neural networks; these are known as neuro-glia networks.
Astrocytes have been shown to facilitate biological self-repair in silent or near silent neurons in the brain by increasing the Probability of Release (PR) in healthy synapses. Astrocytes modulate synaptic activity, which leads to increased or decreased PR. To date, this has been proven with computational modelling and therefore, the next step is to replicate this self-repair process in hardware to provide self-repairing electronic information processing systems. A key challenge for hardware neuro-glia networks implementation is the facilitation of scalable communication between interacting neurons and astrocyte cells. There are large volumes of neurons/astrocytes with different communication patterns and this network is viewed as a two-tiered network:
1. High speed temporal spike event (neural network)
2. Low speed numerical inositol trisphosphate information exchange (astrocyte network)
This thesis addresses the key challenges of providing scalable communication for a neuro-glia network with low-level Networks-on-Chip (NoC) topologies. This network supports astrocyte to neuron/synapse communication at a local level and astrocyte communication at a global level i.e. the astrocyte network. The astrocyte process is inherently slow, thus a ring topology exploits this slow change and sacrifices high throughput for a low area overhead, this is analogous to the astrocyte process. This astrocyte was applied in hardware and results demonstrate that novel ring topology provides a trade-off between low area/interconnect wiring overhead whilst supporting realistic communication speeds for both the slow-changing data between astrocytes and the higher throughput neuron networks.
|Date of Award||Jun 2019|
|Supervisor||Jim Harkin (Supervisor)|
- Neuro-glia Networks
- Networks on Chips
Scalable interconnect strategies for Neuro-glia networks using Networks-on-Chip
Martin, G. (Author). Jun 2019
Student thesis: Doctoral Thesis