A reconfigurable environment for IP cores implementation using dynamic partial reconfiguration

Abstract

Hardware acceleration is becoming increasingly important in high performance applications due to their computational complexity. Recently, field programmable gate arrays (FPGAs) have gained popularity as a suitable platform for many high performance applications. FPGAs offer low power, reconfigurability, high performance and low design turnaround time which enable FPGAs to be used in a number of image and signal processing applications. Due to the increasing complexity of acceleration systems, abstraction of these technologies and power dissipation has become one of the most important challenges. Addressing these issues require awareness at all levels of the system and FPGA design flow. The key achievements of the work presented in this thesis are summarised as follows.

Novel architectures based on different design approaches and abstraction techniques – virtual file systems (VFS), dynamic partial reconfiguration (DPR) mechanism, distributed arithmetic (DA) and parallel digital signal processing – are developed for a generic framework and for three-dimensional (3-D) algorithms. Furthermore, solutions to divide large algorithms into small modules that fit on smaller, less power consuming FPGAs are investigated. An abstraction layer using a VFS for different platforms is carried out, and as a result a partial reconfiguration design flow framework is developed. The ultimate aim of this dissertation is to examine an efficient reconfigurable architecture for generic 3-D cyclic convolution (3-DCC). This is achieved with the previously investigated abstraction layer and framework, to demonstrate the operation of the framework, allowing discussion and the evaluation of techniques that are only possible on new FPGA devices. Results obtained have shown the advantages offered by the DPR framework and abstraction layer, and lead to a processing solution for implementing computationally intensive applications.

A key section of this work included the development of the complete integration of the dynamic partial reconfiguration design flow and application usage – using the proposed abstraction model. The technique used explores the logic space and power consumptions needed to divide the algorithm for optimal application runtime situations.

Date of Award	2012
Original language	English
Supervisor	Abbes Amira (Supervisor)