### Abstract

Language | English |
---|---|

Title of host publication | Unknown Host Publication |

Pages | 597-600 |

Number of pages | 4 |

DOIs | |

Publication status | Published - 2007 |

Event | 2007 International Conference on Field Programmable Logic and Applications - Amsterdam Duration: 1 Jan 2007 → … |

### Conference

Conference | 2007 International Conference on Field Programmable Logic and Applications |
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Period | 1/01/07 → … |

### Fingerprint

### Keywords

- QR
- RLS
- VLSI
- multiplicative division
- mapping architectures

### Cite this

*Unknown Host Publication*(pp. 597-600) https://doi.org/10.1109/FPL.2007.4380725

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*Unknown Host Publication.*pp. 597-600, 2007 International Conference on Field Programmable Logic and Applications, 1/01/07. https://doi.org/10.1109/FPL.2007.4380725

**Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators.** / Lightbody, G; Woods, R; Francey, J.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

AU - Lightbody, G

AU - Woods, R

AU - Francey, J

N1 - Reference text: [1] P. S. Zuchowski et el., “A hybrid ASIC and FPGA architecture” Proc. IEEE/ACM Int’l Conf. on Computer- Aided Design, pp. 187--194, 2002. [2] J. G. McWhirter, “Recursive least squares minimisation using systolic array”, Proc. SPIE (Real-Time Signal Processing IV), vol. 431, pp. 105-112, 1983. [3] R. L. Walke, High Sample Rate Givens Rotations for Recursive Least Squares, PhD Thesis, University of Warwick, 1997. [4] G. Lightbody, R. Woods and R. Walke, “Design of a parameterisable silicon intellectual property core for QR based RLS filtering”, IEEE Trans. on VLSI Systems, vol. 11, No. 4, pp.659-678, August 2003. [5] C. M. Rader “VLSI systolic arrays for adaptive nulling”, IEEE Signal Proc. Mag., vol. 13, no. 4, pp. 29-49, Jul 1996. [6] M. J. Flynn, “On Division by Functional Iteration”, IEEE Trans. on Comp., vol. C-19, No. 8, pp. 702-706, 1970. [7] T. J. Shephard and J. G. McWhirter, “Systolic Adaptive Beamforming”, chapter 5, Array Processing, Eds. S. Haykin, J. Litva and T. J. Shephard, Springer-Verlag, ISBN 3-540-55224, pp. 153-243, 1993. [8] K. D. Tocher, “Techniques of Multiplication and Division for Automatic Binary Computers”, Quart. J. Mech. Appl. Math., vol. XI, Pt. 3, pp364-384, 1958. [9] J. E. Robertson, “A new Class of Division Methods”, IRE Trans. on Electronic Comp., vol. EC-7, pp. 218-222, 1958. [10] M. J. Schulte, J. E. Stine and K. E. Wires, “High-Speed reciprocal Approximations,” Proceedings of the 14th Symposium on Computer Arithmetic, pp. 1183-1187, 1999. [11] “Variable Precision Floating Point Modules” available from NorthEastern University, http://www.ece.neu.edu/groups/ rpl/projects/ floatingpoint/index.html.

PY - 2007

Y1 - 2007

N2 - Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

AB - Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

KW - QR

KW - RLS

KW - VLSI

KW - multiplicative division

KW - mapping architectures

U2 - 10.1109/FPL.2007.4380725

DO - 10.1109/FPL.2007.4380725

M3 - Conference contribution

SN - 978-1-4244-1060-6

SP - 597

EP - 600

BT - Unknown Host Publication

ER -