Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

G Lightbody; R Woods; J Francey

doi:10.1109/FPL.2007.4380725

Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

G Lightbody, R Woods, J Francey

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

212 Downloads (Pure)

Abstract

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

Original language	English
Title of host publication	Unknown Host Publication
Publisher	IEEE
Pages	597-600
Number of pages	4
ISBN (Print)	978-1-4244-1060-6
DOIs	https://doi.org/10.1109/FPL.2007.4380725
Publication status	Published (in print/issue) - 2007
Event	2007 International Conference on Field Programmable Logic and Applications - Amsterdam Duration: 1 Jan 2007 → …

Conference

Conference	2007 International Conference on Field Programmable Logic and Applications
Period	1/01/07 → …

Bibliographical note

Reference text: [1] P. S. Zuchowski et el., “A hybrid ASIC and FPGA architecture” Proc. IEEE/ACM Int’l Conf. on Computer- Aided Design, pp. 187--194, 2002.
[2] J. G. McWhirter, “Recursive least squares minimisation using systolic array”, Proc. SPIE (Real-Time Signal Processing IV), vol. 431, pp. 105-112, 1983.
[3] R. L. Walke, High Sample Rate Givens Rotations for Recursive Least Squares, PhD Thesis, University of Warwick, 1997.
[4] G. Lightbody, R. Woods and R. Walke, “Design of a parameterisable silicon intellectual property core for QR based RLS filtering”, IEEE Trans. on VLSI Systems, vol. 11, No. 4, pp.659-678, August 2003.
[5] C. M. Rader “VLSI systolic arrays for adaptive nulling”, IEEE Signal Proc. Mag., vol. 13, no. 4, pp. 29-49, Jul 1996.
[6] M. J. Flynn, “On Division by Functional Iteration”, IEEE Trans. on Comp., vol. C-19, No. 8, pp. 702-706, 1970.
[7] T. J. Shephard and J. G. McWhirter, “Systolic Adaptive Beamforming”, chapter 5, Array Processing, Eds. S. Haykin, J. Litva and T. J. Shephard, Springer-Verlag, ISBN 3-540-55224, pp. 153-243, 1993.
[8] K. D. Tocher, “Techniques of Multiplication and Division for Automatic Binary Computers”, Quart. J. Mech. Appl. Math., vol. XI, Pt. 3, pp364-384, 1958.
[9] J. E. Robertson, “A new Class of Division Methods”, IRE Trans. on Electronic Comp., vol. EC-7, pp. 218-222, 1958.
[10] M. J. Schulte, J. E. Stine and K. E. Wires, “High-Speed reciprocal Approximations,” Proceedings of the 14th Symposium on Computer Arithmetic, pp. 1183-1187, 1999.
[11] “Variable Precision Floating Point Modules” available from NorthEastern University, http://www.ece.neu.edu/groups/ rpl/projects/ floatingpoint/index.html.

Keywords

QR
RLS
VLSI
multiplicative division
mapping architectures

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10.1109/FPL.2007.4380725

FPL2007 LightbodyQRFinal published version, 835 KB

Cite this

@inproceedings{dd37b82c99714c9c8d7efd5c4f567456,

title = "Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators",

abstract = "Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.",

keywords = "QR, RLS, VLSI, multiplicative division, mapping architectures",

author = "G Lightbody and R Woods and J Francey",

note = "Reference text: [1] P. S. Zuchowski et el., “A hybrid ASIC and FPGA architecture” Proc. IEEE/ACM Int{\textquoteright}l Conf. on Computer- Aided Design, pp. 187--194, 2002. [2] J. G. McWhirter, “Recursive least squares minimisation using systolic array”, Proc. SPIE (Real-Time Signal Processing IV), vol. 431, pp. 105-112, 1983. [3] R. L. Walke, High Sample Rate Givens Rotations for Recursive Least Squares, PhD Thesis, University of Warwick, 1997. [4] G. Lightbody, R. Woods and R. Walke, “Design of a parameterisable silicon intellectual property core for QR based RLS filtering”, IEEE Trans. on VLSI Systems, vol. 11, No. 4, pp.659-678, August 2003. [5] C. M. Rader “VLSI systolic arrays for adaptive nulling”, IEEE Signal Proc. Mag., vol. 13, no. 4, pp. 29-49, Jul 1996. [6] M. J. Flynn, “On Division by Functional Iteration”, IEEE Trans. on Comp., vol. C-19, No. 8, pp. 702-706, 1970. [7] T. J. Shephard and J. G. McWhirter, “Systolic Adaptive Beamforming”, chapter 5, Array Processing, Eds. S. Haykin, J. Litva and T. J. Shephard, Springer-Verlag, ISBN 3-540-55224, pp. 153-243, 1993. [8] K. D. Tocher, “Techniques of Multiplication and Division for Automatic Binary Computers”, Quart. J. Mech. Appl. Math., vol. XI, Pt. 3, pp364-384, 1958. [9] J. E. Robertson, “A new Class of Division Methods”, IRE Trans. on Electronic Comp., vol. EC-7, pp. 218-222, 1958. [10] M. J. Schulte, J. E. Stine and K. E. Wires, “High-Speed reciprocal Approximations,” Proceedings of the 14th Symposium on Computer Arithmetic, pp. 1183-1187, 1999. [11] “Variable Precision Floating Point Modules” available from NorthEastern University, http://www.ece.neu.edu/groups/ rpl/projects/ floatingpoint/index.html.; 2007 International Conference on Field Programmable Logic and Applications ; Conference date: 01-01-2007",

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AB - Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

KW - QR

KW - RLS

KW - VLSI

KW - multiplicative division

KW - mapping architectures

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DO - 10.1109/FPL.2007.4380725

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BT - Unknown Host Publication

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Y2 - 1 January 2007

ER -

Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

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Bibliographical note

Keywords

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