Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

G Lightbody, R Woods, J Francey

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
46 Downloads (Pure)

Abstract

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.
Original languageEnglish
Title of host publicationUnknown Host Publication
PublisherIEEE
Pages597-600
Number of pages4
ISBN (Print)978-1-4244-1060-6
DOIs
Publication statusPublished - 2007
Event2007 International Conference on Field Programmable Logic and Applications - Amsterdam
Duration: 1 Jan 2007 → …

Conference

Conference2007 International Conference on Field Programmable Logic and Applications
Period1/01/07 → …

Keywords

  • QR
  • RLS
  • VLSI
  • multiplicative division
  • mapping architectures

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