Smart Watchdog Mechanism for Fault Detection in RISC-V

David Simpson; Jim Harkin; Malachy McElholm; LJ McDaid

doi:10.1109/ISCAS56072.2025.11044018

Smart Watchdog Mechanism for Fault Detection in RISC-V

David Simpson, Jim Harkin, Malachy McElholm, LJ McDaid

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Abstract

Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	979-8-3503-5683-0
ISBN (Print)	979-8-3503-5684-7
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11044018
Publication status	Published (in print/issue) - 27 Jun 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Funding

Department for Economy (DfE)

Keywords

Watchdog
spiking neural networks
Neuromorphic circuits
Fault Detection
Spiking neural network
RISC-V

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS56072.2025.11044018

Final Paper ApprovedAuthor Accepted Manuscript -, 754 KB

Cite this

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title = "Smart Watchdog Mechanism for Fault Detection in RISC-V",

abstract = "Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98\%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.",

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Smart Watchdog Mechanism for Fault Detection in RISC-V. / Simpson, David ; Harkin, Jim ; McElholm, Malachy et al.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. IEEE, 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Smart Watchdog Mechanism for Fault Detection in RISC-V

AU - Simpson, David

AU - Harkin, Jim

AU - McElholm, Malachy

AU - McDaid, LJ

PY - 2025/6/27

Y1 - 2025/6/27

N2 - Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.

AB - Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.

KW - Watchdog

KW - spiking neural networks

KW - Neuromorphic circuits

KW - Fault Detection

KW - Spiking neural network

KW - RISC-V

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UR - https://www.scopus.com/pages/publications/105010584812

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DO - 10.1109/ISCAS56072.2025.11044018

M3 - Conference contribution

SN - 979-8-3503-5684-7

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings

PB - IEEE

ER -

Smart Watchdog Mechanism for Fault Detection in RISC-V

Abstract

Publication series

Bibliographical note

Funding

Keywords

UN SDGs

Access to Document

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Live Demonstration: Smart Watchdog Mechanism for Real-time Fault Detection in RISC-V

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