TY - JOUR
T1 - Silicon-Based Dynamic Synapse With Depressing Response
AU - Dowrick, Thomas
AU - Hall, Steve
AU - McDaid, Liam
PY - 2012/10/10
Y1 - 2012/10/10
N2 - A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is “weighted” by a voltage applied to the secondterminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltagedetermines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal–oxide–semiconductor field-effect transistor operatingin subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal–oxide–semiconductor process, alongside theoretical and simulation results, confirm the abilityof the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.
AB - A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is “weighted” by a voltage applied to the secondterminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltagedetermines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal–oxide–semiconductor field-effect transistor operatingin subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal–oxide–semiconductor process, alongside theoretical and simulation results, confirm the abilityof the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.
U2 - 10.1109/TNNLS.2012.2211035
DO - 10.1109/TNNLS.2012.2211035
M3 - Article
VL - 23
SP - 1513
EP - 1525
JO - IEEE Transactions on Neural Networks and Learning Systems
JF - IEEE Transactions on Neural Networks and Learning Systems
SN - 2162-237X
IS - 10
ER -
