Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks

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Abstract

Spiking astrocyte-neuron networks (ANNs) have the potential to emulate the self-repair capability in the mammalian brain. Recent research has explored the mimicking of this capability in hardware with the aim to make electronic circuits autonomous with self-detection and repair. The provision of hardware architectures and interconnectivity between the massive numbers of spiking neurons and astrocytes is a significant research challenge, as the neuron and astrocyte networks have different communication patterns. In particular they have large volumes of information exchanges. This paper presents a novel interconnected architecture for ANN hardware systems based on the hierarchical astrocyte network architecture (HANA). HANA supports the information exchanges between astrocyte cells and addresses the interconnection challenge by providing a novel hierarchical networks-on-chip (NoC) structure of neurons and astrocytes cells. The proposed HANA incorporates a priority scheduling mechanism to increase the information exchange rate for global astrocyte cells, thus reducing the global communication latency and providing a balance between the local and global astrocyte network traffic. Experimental results demonstrate that the proposed HANA architecture can provide efficient information exchange rates for ANN, while the hardware synthesis results demonstrates that it has a low area utilization and power consumption which supports scalability.
Original languageEnglish
Pages (from-to)2290-2303
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume63
Issue number12
DOIs
Publication statusPublished - 23 Nov 2016

Keywords

  • Spiking neural networks
  • astrocyte
  • networks-on-chip
  • hierarchical
  • self-repair
  • fault tolerance
  • FPGA.

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