Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations

S Carrillo; Jim Harkin; Liam McDaid; F Morgan; S Pande; S Cawley; B McGinley

doi:10.1109/TPDS.2012.289

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations

S Carrillo
, Jim Harkin
, Liam McDaid
, F Morgan
, S Pande
, S Cawley
, B McGinley

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	2451-2461
Journal	IEEE Transactions on Parallel and Distributed Systems
Volume	24
Issue number	12
DOIs	https://doi.org/10.1109/TPDS.2012.289
Publication status	Published (in print/issue) - Dec 2013

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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10.1109/TPDS.2012.289

http://www.computer.org/portal/web/tpds

Scalable hierarchical networks-on-chip architecture for brain-inspired computing
Carrillo Lindado, S. (Author), Harkin, J. (Supervisor) & McDaid, L. (Supervisor), Jan 2013
Student thesis: Doctoral Thesis

File

Cite this

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title = "Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations",

author = "S Carrillo and Jim Harkin and Liam McDaid and F Morgan and S Pande and S Cawley and B McGinley",

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TY - JOUR

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AU - Carrillo, S

AU - Harkin, Jim

AU - McDaid, Liam

AU - Morgan, F

AU - Pande, S

AU - Cawley, S

AU - McGinley, B

PY - 2013/12

Y1 - 2013/12

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DO - 10.1109/TPDS.2012.289

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JO - IEEE Transactions on Parallel and Distributed Systems

JF - IEEE Transactions on Parallel and Distributed Systems

IS - 12

ER -

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations

UN SDGs

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Student theses

Scalable hierarchical networks-on-chip architecture for brain-inspired computing

Cite this