Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations

S Carrillo, Jim Harkin, Liam McDaid, F Morgan, S Pande, S Cawley, B McGinley

Research output: Contribution to journalArticle

56 Citations (Scopus)
LanguageEnglish
Pages2451-2461
JournalIEEE Transactions on Parallel and Distributed Systems
Volume24
Issue number12
DOIs
Publication statusPublished - Dec 2013

Cite this

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title = "Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations",
author = "S Carrillo and Jim Harkin and Liam McDaid and F Morgan and S Pande and S Cawley and B McGinley",
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Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware implementations. / Carrillo, S; Harkin, Jim; McDaid, Liam; Morgan, F; Pande, S; Cawley, S; McGinley, B.

In: IEEE Transactions on Parallel and Distributed Systems, Vol. 24, No. 12, 12.2013, p. 2451-2461.

Research output: Contribution to journalArticle

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AU - Carrillo, S

AU - Harkin, Jim

AU - McDaid, Liam

AU - Morgan, F

AU - Pande, S

AU - Cawley, S

AU - McGinley, B

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JF - IEEE Transactions on Parallel and Distributed Systems

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