Rapid design of a single chip adaptive beamformer

G Lightbody, R. Woods, J. McCanny, R. Walke, Y. Hu, D. Trainor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of alibrary of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.
LanguageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationOnline
Pages285-294
Number of pages10
DOIs
Publication statusPublished - 6 Aug 2002
EventSignal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on - Cambridge, MA , USA
Duration: 6 Aug 2002 → …

Workshop

WorkshopSignal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Period6/08/02 → …

Fingerprint

Integrated circuit layout
Parallel processing systems
Transistors
Silicon
Networks (circuits)
Intellectual property core

Keywords

  • QR
  • RLS
  • Systolic array
  • VLSI

Cite this

Lightbody, G., Woods, R., McCanny, J., Walke, R., Hu, Y., & Trainor, D. (2002). Rapid design of a single chip adaptive beamformer. In Unknown Host Publication (pp. 285-294). Online. https://doi.org/10.1109/SIPS.1998.715791
Lightbody, G ; Woods, R. ; McCanny, J. ; Walke, R. ; Hu, Y. ; Trainor, D. / Rapid design of a single chip adaptive beamformer. Unknown Host Publication. Online, 2002. pp. 285-294
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abstract = "This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of alibrary of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.",
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author = "G Lightbody and R. Woods and J. McCanny and R. Walke and Y. Hu and D. Trainor",
note = "Reference text: [ 11 Kalouptsidis and Theodoridis, Adaptive System Identzjcation and Signal Processing Algorithms, Prentice Hall, Englewood Cliffs, NJ, 1993 [2] S. Haykin, Adaptive Filter Theory, Prentice Hall: Englewood Cliffs, NJ, 1986. [3] W. M. Gentleman and H. T. Kung, “Matrix triangularisation by systolic array”, Proc. SPIE (Real-Time Signal Processing Iv), pp.329-369, 1973. [4] J. G. McWhirter, “Recursive least squares minimisation using systolic array”, Proc. SPIE (Real-Time Signal Processing I v , vol. 431, pp. 105-1 12, 1983. [5] J. M. Cioffi and T. Kailath, “Fast recursive-least-square, transversal filters for adaptive filtering,” IEEE Trans. Acoustics, Speech, Signal Processing, vol. [6] S. F. Hsieh, K. J. R. Liu and K. Yao, “A Unified Approach for QRD-Based Recursive Least-Squares Estimation without Square Roots”, IEEE Trans. On Signal Processing, Vol. 41, No. 3, pp. 1405-1409, March 1993. [7] R. L. Walke, High Sample Rate Givens Rotations for Recursive Least Squares, Thesis, University of Warwick, 1997 [8] J. V. McCanny, D. Ridge, Y. Hu, J. Hunter, “Hierarchical VHDL libraries for DSP ASIC design”, ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing, proceedings, vol. 1, pp. 675-678, 1997. [9] C. M. Rader “ VLSI systolic arrays for adaptive nulling”, IEEE Signal Processing Magazine, Vol. 13, No. 4, pp. 29-49, Jul 1996 [10] L. C. Godara, “Application of antenna arrays to mobile communications, part II: Beam-forming and direction-of-arrival considerations”, Proc. of the IEEE, [11] T. J. Shephard and J. G. McWhirter, “Systolic Adaptive Beamforming”, chap. 5, Array Processing, Eds. S. Hayh, J. Litva and T. J. Shephard, Springer-Verlag, ISBN 3-540-55224, pp. 153-243, 1993. [12] J. G. McWhirter, R. L. Walke and J. Kadlec, “Normalised Givens Rotations for Recursive Least Squares Processing”, VLSI Signal Processing, VIZ4 .ISBN ASSP-32, NO. 2, pp. 998-1005, 1984. [13] R. Dohler, “Squared Given’s Rotations”, IMA J. of Numerical Analysis, Vol. Vol. 85, NO. 8, pp. 1195-1245, Aug. 1997. [14] A. Wenzler, E. Lueder, “New structures for complex multipliers and their noise analysis”, Proc.- IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1432-1435, 1995. [15] D. W. Trainor, R. F. Woods, J. V. McCanny, “Architectural Synthesis of Digital Signal Processing Algorithms using ‘IRIS’ ”, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 16, No. 1, pp. 41-55, May 1997.",
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Lightbody, G, Woods, R, McCanny, J, Walke, R, Hu, Y & Trainor, D 2002, Rapid design of a single chip adaptive beamformer. in Unknown Host Publication. Online, pp. 285-294, Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on, 6/08/02. https://doi.org/10.1109/SIPS.1998.715791

Rapid design of a single chip adaptive beamformer. / Lightbody, G; Woods, R.; McCanny, J.; Walke, R.; Hu, Y.; Trainor, D.

Unknown Host Publication. Online, 2002. p. 285-294.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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KW - VLSI

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Lightbody G, Woods R, McCanny J, Walke R, Hu Y, Trainor D. Rapid design of a single chip adaptive beamformer. In Unknown Host Publication. Online. 2002. p. 285-294 https://doi.org/10.1109/SIPS.1998.715791