This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of alibrary of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.
|Title of host publication||Unknown Host Publication|
|Place of Publication||Online|
|Number of pages||10|
|Publication status||Published (in print/issue) - 6 Aug 2002|
|Event||Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on - Cambridge, MA , USA|
Duration: 6 Aug 2002 → …
|Workshop||Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on|
|Period||6/08/02 → …|
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- Systolic array