QR Recursive Least Squares IP Core Example

Gaye Lightbody, Roger Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

With transistor counts increasing at a rate of 58%per year and design productivity only growing at 21%per year, there is an important need to develop newdesign approaches to close this gap. This paper outlinesthe process by which IP cores are generated and showshow the design methodology can be improved to enhancetheir usability. The process is demonstrated using arecursive least squares (RLS) adaptive lter example.
LanguageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationWashington, DC, USA
Pages369-374
Number of pages6
DOIs
Publication statusPublished - 18 Apr 2008
EventECBS '08: Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems - Belfast
Duration: 18 Apr 2008 → …

Conference

ConferenceECBS '08: Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems
Period18/04/08 → …

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Transistors
Productivity
Intellectual property core

Cite this

Lightbody, G., & Woods, R. (2008). QR Recursive Least Squares IP Core Example. In Unknown Host Publication (pp. 369-374). Washington, DC, USA. https://doi.org/10.1109/ECBS.2008.54
Lightbody, Gaye ; Woods, Roger. / QR Recursive Least Squares IP Core Example. Unknown Host Publication. Washington, DC, USA, 2008. pp. 369-374
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abstract = "With transistor counts increasing at a rate of 58{\%}per year and design productivity only growing at 21{\%}per year, there is an important need to develop newdesign approaches to close this gap. This paper outlinesthe process by which IP cores are generated and showshow the design methodology can be improved to enhancetheir usability. The process is demonstrated using arecursive least squares (RLS) adaptive lter example.",
author = "Gaye Lightbody and Roger Woods",
note = "Reference text: [1] A. Allan, H. William, and B. Andrew. Technology Roadmap for Semiconductors, 2001. [2] S. I. Association. International technology roadmap for semiconductors: Design, 2005. [3] D. Gajski, A.-H. Wu, V. Chaiyakul, S. Mori, T. Nukiyama, and P. Bricaud. Essential issues for IP reuse. Proc. of the ASP-DAC, pages 37-42, 2000. [4] Y. Huang, W. Cheng, C. Tsai, N. Mukherjee, O. Sam-man, Y. Zaidan, and S. Reddy. Resource Alloca-tion and Test Scheduling for Concurrent Test of Core-Based SOC Design. Proceedings of IEEE Asian Test Symposium (ATS), pages 265-270, 2001. [5] L. Jianwen and J. C. Chuen. Matrix inversion on reconfgurable hardware using binary-coded z-path cordic. In Proc. of the IEEE Asia Pacfc Conferenceon Circuits and Systems, pages 1176-1179, Dec. 2006. [6] S. Kung. VLSI Array processors. ASSP Magazine, IEEE [see also IEEE Signal Processing Magazine], 2(3):4-22, 1985. [7] G. Lightbody, R. Woods, and J. Francey. Soft IP core implementation of Recursive Least Squares filter using only multiplicative and additive operators. In Proc. of IEEE Int'l Conf. on FPL, pages 597-600, Aug. 2007. [8] G. Lightbody, R. Woods, and R. Walke. Design of a parameterizable silicon intellectual property core for QR-based RLS fltering. IEEE Trans. on VLSI Systems, 11(4):659-678, 2003. [9] J. McWhirter. Recursive least-squares minimization using a systolic array. Proc. SPIE, 431:105-109, 1983. [10] G. Moretti. Your core, my design, our problem, EDN, 2001. [11] S. F. Obermann and M. J. Flynn. A new Class of Division Methods. Trans. on Computers, 46(8):833-854, 1997. [12] C. Rader. VLSI systolic arrays for adaptive nulling. Signal Processing Magazine, IEEE, 13(4):29-49, 1996. [13] C. Rowen. Reducing SoC simulation and development time. Computer, 35(12):29-34, 2002. [14] P. Varma and S. Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. Proceedings IEEE International Test Conference (ITC), pages 294-302, 1998. [15] R. Walke. High sample rate givens rotations for recursive least squares. PhD thesis, Ph. D. Thesis, University of Warwick, 1997, 1997.",
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Lightbody, G & Woods, R 2008, QR Recursive Least Squares IP Core Example. in Unknown Host Publication. Washington, DC, USA, pp. 369-374, ECBS '08: Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, 18/04/08. https://doi.org/10.1109/ECBS.2008.54

QR Recursive Least Squares IP Core Example. / Lightbody, Gaye; Woods, Roger.

Unknown Host Publication. Washington, DC, USA, 2008. p. 369-374.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lightbody G, Woods R. QR Recursive Least Squares IP Core Example. In Unknown Host Publication. Washington, DC, USA. 2008. p. 369-374 https://doi.org/10.1109/ECBS.2008.54