With transistor counts increasing at a rate of 58%per year and design productivity only growing at 21%per year, there is an important need to develop newdesign approaches to close this gap. This paper outlinesthe process by which IP cores are generated and showshow the design methodology can be improved to enhancetheir usability. The process is demonstrated using arecursive least squares (RLS) adaptive lter example.
|Title of host publication||Unknown Host Publication|
|Place of Publication||Washington, DC, USA|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|Publication status||Published (in print/issue) - 18 Apr 2008|
|Event||ECBS '08: Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems - Belfast|
Duration: 18 Apr 2008 → …
|Conference||ECBS '08: Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems|
|Period||18/04/08 → …|
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