Power modeling and efficient FPGA implementation of FHT for signal processing

A Amira, S Chandrasekaran

    Research output: Contribution to journalArticle

    22 Citations (Scopus)

    Abstract

    Fast Hadamard transform (FHT) belongs to the family of discrete orthogonal transforms and is used widely in image and signal processing applications. In this paper, a parameterizable and scalable architecture for FHT with time and area complexities of O(2(W + 1)) and O(2N(2)), respectively, has been proposed, where W and N are the word and vector lengths. A novel algorithmic transformation for the FHT based on sparse matrix factorization and distributed arithmetic (DA) principles has been presented. The architecture has been parallelized and pipelined in order to achieve high throughput rates. Efficient and optimized field-programmable gate array implementation of the proposed architecture that yield excellent performance metrics has been analyzed in detail. Additionally, a functional level power analysis and modeling methodology has been proposed to characterize the various power and energy metrics of the cores in terms of system parameters and design variables. The mathematical models that have been derived provide quick presilicon estimate of power and energy measures, allowing intelligent tradeoffs when incorporating the developed cores as subblocks in hardware-based image and video processing systems.
    LanguageEnglish
    Pages286-295
    JournalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    Volume15
    Issue number3
    DOIs
    Publication statusPublished - Mar 2007

    Fingerprint

    Hadamard transforms
    Field programmable gate arrays (FPGA)
    Signal processing
    Factorization
    Image processing
    Throughput
    Mathematical models
    Hardware
    Processing

    Keywords

    • discrete orthogonal transforms (DOTs)
    • distributed arithmetic
    • fast Hadamard transform (FHT)
    • field-programmable gate array (FPGA)
    • power
    • modeling
    • sparse matrices

    Cite this

    Amira, A ; Chandrasekaran, S. / Power modeling and efficient FPGA implementation of FHT for signal processing. 2007 ; Vol. 15, No. 3. pp. 286-295.
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    Power modeling and efficient FPGA implementation of FHT for signal processing. / Amira, A; Chandrasekaran, S.

    Vol. 15, No. 3, 03.2007, p. 286-295.

    Research output: Contribution to journalArticle

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    T1 - Power modeling and efficient FPGA implementation of FHT for signal processing

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    AU - Chandrasekaran, S

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    AB - Fast Hadamard transform (FHT) belongs to the family of discrete orthogonal transforms and is used widely in image and signal processing applications. In this paper, a parameterizable and scalable architecture for FHT with time and area complexities of O(2(W + 1)) and O(2N(2)), respectively, has been proposed, where W and N are the word and vector lengths. A novel algorithmic transformation for the FHT based on sparse matrix factorization and distributed arithmetic (DA) principles has been presented. The architecture has been parallelized and pipelined in order to achieve high throughput rates. Efficient and optimized field-programmable gate array implementation of the proposed architecture that yield excellent performance metrics has been analyzed in detail. Additionally, a functional level power analysis and modeling methodology has been proposed to characterize the various power and energy metrics of the cores in terms of system parameters and design variables. The mathematical models that have been derived provide quick presilicon estimate of power and energy measures, allowing intelligent tradeoffs when incorporating the developed cores as subblocks in hardware-based image and video processing systems.

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    KW - sparse matrices

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