Abstract
Hardware has become more prone to faults as a result of geometric scaling, wear-out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self-repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self-repair within models of neural networks known as neuro-glia networks. This astrocyte-driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro-glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine-grained self-repair process. Therefore, mapping neuro-glia networks to hardware provides a strategy for achieving self-repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self-repair process is dependent on the communication infrastructure between astrocyte-to-astrocyte; e.g. astrocyte network. This study addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements.
Original language | English |
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Pages (from-to) | 130-138 |
Number of pages | 9 |
Journal | IET Computers and Digital Techniques |
Volume | 12 |
Issue number | 4 |
Early online date | 8 May 2018 |
DOIs | |
Publication status | Published (in print/issue) - 1 Jul 2018 |
Keywords
- Integrated circuit interconnections
- Neural chips
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John Wade
- School of Computing, Eng & Intel. Sys - Lecturer in Computer Science
- Faculty Of Computing, Eng. & Built Env. - Lecturer
Person: Academic