Novel FPGA implementations of Walsh-Hadamard transforms for signal processing

A Amira, A Bouridane, P Milligan, M Roula

    Research output: Contribution to journalArticle

    28 Citations (Scopus)

    Abstract

    The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.
    LanguageEnglish
    Pages377-383
    JournalIEE Proceedings - Vision Image and Signal Processing
    Volume148
    Issue number6
    DOIs
    Publication statusPublished - Dec 2001

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    Walsh transforms
    Hadamard transforms
    Field programmable gate arrays (FPGA)
    Signal processing
    ROM
    Factorization

    Cite this

    Amira, A ; Bouridane, A ; Milligan, P ; Roula, M. / Novel FPGA implementations of Walsh-Hadamard transforms for signal processing. In: IEE Proceedings - Vision Image and Signal Processing. 2001 ; Vol. 148, No. 6. pp. 377-383.
    @article{1cf51b9bcc2246d8ba09b13dd6d9fd3b,
    title = "Novel FPGA implementations of Walsh-Hadamard transforms for signal processing",
    abstract = "The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.",
    author = "A Amira and A Bouridane and P Milligan and M Roula",
    year = "2001",
    month = "12",
    doi = "10.1049/ip-vis:20010674",
    language = "English",
    volume = "148",
    pages = "377--383",
    journal = "IEE Proceedings - Vision Image and Signal Processing",
    issn = "1350-245X",
    number = "6",

    }

    Novel FPGA implementations of Walsh-Hadamard transforms for signal processing. / Amira, A; Bouridane, A; Milligan, P; Roula, M.

    In: IEE Proceedings - Vision Image and Signal Processing, Vol. 148, No. 6, 12.2001, p. 377-383.

    Research output: Contribution to journalArticle

    TY - JOUR

    T1 - Novel FPGA implementations of Walsh-Hadamard transforms for signal processing

    AU - Amira, A

    AU - Bouridane, A

    AU - Milligan, P

    AU - Roula, M

    PY - 2001/12

    Y1 - 2001/12

    N2 - The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.

    AB - The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.

    U2 - 10.1049/ip-vis:20010674

    DO - 10.1049/ip-vis:20010674

    M3 - Article

    VL - 148

    SP - 377

    EP - 383

    JO - IEE Proceedings - Vision Image and Signal Processing

    T2 - IEE Proceedings - Vision Image and Signal Processing

    JF - IEE Proceedings - Vision Image and Signal Processing

    SN - 1350-245X

    IS - 6

    ER -