The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.
|Journal||IEE Proceedings - Vision Image and Signal Processing|
|Publication status||Published - Dec 2001|
Amira, A., Bouridane, A., Milligan, P., & Roula, M. (2001). Novel FPGA implementations of Walsh-Hadamard transforms for signal processing. IEE Proceedings - Vision Image and Signal Processing, 148(6), 377-383. https://doi.org/10.1049/ip-vis:20010674