New pipelined digit serial-parallel multiplier

O. Nibouche; A. Bouridane; M. Nibouche; D. Crookes

doi:10.1109/ISCAS.2000.857013

New pipelined digit serial-parallel multiplier

O. Nibouche, A. Bouridane, M. Nibouche, D. Crookes

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

A new algorithm for digit serial-parallel multiplication was presented. The multipliers derived from this algorithm can be pipelined at the bit-level by using a multiple pipes architecture. This is achieved by making independent the multiplication of each sub-digit by the multiplier from one side, and by making the accumulation of the partial results independent from their generation on the other side. The analysis of the proposed multiplier based on the effect of the digit size and the level of pipelining for a 32-bit multiplier has shown that the multiplier is as speed as the level pipelining is going towards the bit-level at a cost of an increasing area.

Original language	English
Pages (from-to)	I-12-I-15
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.2000.857013
Publication status	Published (in print/issue) - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

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10.1109/ISCAS.2000.857013

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abstract = "A new algorithm for digit serial-parallel multiplication was presented. The multipliers derived from this algorithm can be pipelined at the bit-level by using a multiple pipes architecture. This is achieved by making independent the multiplication of each sub-digit by the multiplier from one side, and by making the accumulation of the partial results independent from their generation on the other side. The analysis of the proposed multiplier based on the effect of the digit size and the level of pipelining for a 32-bit multiplier has shown that the multiplier is as speed as the level pipelining is going towards the bit-level at a cost of an increasing area.",

author = "O. Nibouche and A. Bouridane and M. Nibouche and D. Crookes",

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doi = "10.1109/ISCAS.2000.857013",

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T1 - New pipelined digit serial-parallel multiplier

AU - Nibouche, O.

AU - Bouridane, A.

AU - Nibouche, M.

AU - Crookes, D.

PY - 2000

Y1 - 2000

N2 - A new algorithm for digit serial-parallel multiplication was presented. The multipliers derived from this algorithm can be pipelined at the bit-level by using a multiple pipes architecture. This is achieved by making independent the multiplication of each sub-digit by the multiplier from one side, and by making the accumulation of the partial results independent from their generation on the other side. The analysis of the proposed multiplier based on the effect of the digit size and the level of pipelining for a 32-bit multiplier has shown that the multiplier is as speed as the level pipelining is going towards the bit-level at a cost of an increasing area.

AB - A new algorithm for digit serial-parallel multiplication was presented. The multipliers derived from this algorithm can be pipelined at the bit-level by using a multiple pipes architecture. This is achieved by making independent the multiplication of each sub-digit by the multiplier from one side, and by making the accumulation of the partial results independent from their generation on the other side. The analysis of the proposed multiplier based on the effect of the digit size and the level of pipelining for a 32-bit multiplier has shown that the multiplier is as speed as the level pipelining is going towards the bit-level at a cost of an increasing area.

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U2 - 10.1109/ISCAS.2000.857013

DO - 10.1109/ISCAS.2000.857013

M3 - Conference article

AN - SCOPUS:0033685459

SN - 0271-4310

VL - 1

SP - I-12-I-15

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

New pipelined digit serial-parallel multiplier

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