Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network

S Pande, F Morgan, S Cawley, T Bruintjes, G Smit, B McGinley, S Carrillo, J Harkin, L McDaid

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

Biologically-inspired packet switched Network on Chip (NoC) basedhardware Spiking Neural Network (SNN) architectures have been proposed asan embedded computing platform for classi cation, estimation and control ap-plications. Storage of large synaptic connectivity (SNN topology) information inSNNs require large distributed on-chip memory, which poses serious challenges forcompact hardware implementation of such architectures. Based on the structuredneural organisation observed in human brain, a Modular Neural Networks (MNN)design strategy partitions complex application tasks into smaller subtasks execut-ing on distinct neural network modules, and integrates intermediate outputs inhigher level functions.This paper proposes a hardware Modular Neural Tile (MNT) architecture thatreduces the SNN topology memory requirement of NoC-based hardware SNNs byusing a combination of xed and con gurable synaptic connections. The proposedMNT contains a 16:16 fully-connected feed-forward SNN structure and integratesin a mesh topology NoC communication infrastructure. The SNN topology memoryrequirement is 50% of the monolithic NoC-based hardware SNN implementation.The paper also presents a lookup table based SNN topology memory allocationtechnique, which further increases the memory utilisation eciency. Overall thearea requirement of the architecture is reduced by an average of 66% for practicalSNN application topologies.The paper presents micro-architecture details of the proposed MNT and digitalneuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. The evolvablecapability of the proposed MNT and its suitability for executing subtasks within aMNN execution architecture is demonstrated by successfully evolving benchmarkSNN application tasks representing classi cation and non-linear control functions.The paper addresses hardware modular SNN design and implementation chal-lenges and contributes to the development of a compact hardware modular SNNarchitecture suitable for embedded applications.
LanguageEnglish
Pages131-153
JournalNeural Processing Letters
Volume38
Issue number2
DOIs
Publication statusPublished - Oct 2013

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Tile
Neural networks
Hardware
Topology
Data storage equipment
Computer hardware
Positive ions
Table lookup
Packet networks
Feedforward neural networks
Network architecture
Field programmable gate arrays (FPGA)
Brain
Network-on-chip
Networks (circuits)
Communication

Cite this

Pande, S ; Morgan, F ; Cawley, S ; Bruintjes, T ; Smit, G ; McGinley, B ; Carrillo, S ; Harkin, J ; McDaid, L. / Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network. In: Neural Processing Letters. 2013 ; Vol. 38, No. 2. pp. 131-153.
@article{089c8a7505424f19ac9a70e112ec10a8,
title = "Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network",
abstract = "Biologically-inspired packet switched Network on Chip (NoC) basedhardware Spiking Neural Network (SNN) architectures have been proposed asan embedded computing platform for classi cation, estimation and control ap-plications. Storage of large synaptic connectivity (SNN topology) information inSNNs require large distributed on-chip memory, which poses serious challenges forcompact hardware implementation of such architectures. Based on the structuredneural organisation observed in human brain, a Modular Neural Networks (MNN)design strategy partitions complex application tasks into smaller subtasks execut-ing on distinct neural network modules, and integrates intermediate outputs inhigher level functions.This paper proposes a hardware Modular Neural Tile (MNT) architecture thatreduces the SNN topology memory requirement of NoC-based hardware SNNs byusing a combination of xed and con gurable synaptic connections. The proposedMNT contains a 16:16 fully-connected feed-forward SNN structure and integratesin a mesh topology NoC communication infrastructure. The SNN topology memoryrequirement is 50{\%} of the monolithic NoC-based hardware SNN implementation.The paper also presents a lookup table based SNN topology memory allocationtechnique, which further increases the memory utilisation eciency. Overall thearea requirement of the architecture is reduced by an average of 66{\%} for practicalSNN application topologies.The paper presents micro-architecture details of the proposed MNT and digitalneuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. The evolvablecapability of the proposed MNT and its suitability for executing subtasks within aMNN execution architecture is demonstrated by successfully evolving benchmarkSNN application tasks representing classi cation and non-linear control functions.The paper addresses hardware modular SNN design and implementation chal-lenges and contributes to the development of a compact hardware modular SNNarchitecture suitable for embedded applications.",
author = "S Pande and F Morgan and S Cawley and T Bruintjes and G Smit and B McGinley and S Carrillo and J Harkin and L McDaid",
year = "2013",
month = "10",
doi = "10.1007/s11063-012-9274-5",
language = "English",
volume = "38",
pages = "131--153",
journal = "Neural Processing Letters",
issn = "1370-4621",
number = "2",

}

Pande, S, Morgan, F, Cawley, S, Bruintjes, T, Smit, G, McGinley, B, Carrillo, S, Harkin, J & McDaid, L 2013, 'Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network', Neural Processing Letters, vol. 38, no. 2, pp. 131-153. https://doi.org/10.1007/s11063-012-9274-5

Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network. / Pande, S; Morgan, F; Cawley, S; Bruintjes, T; Smit, G; McGinley, B; Carrillo, S; Harkin, J; McDaid, L.

In: Neural Processing Letters, Vol. 38, No. 2, 10.2013, p. 131-153.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network

AU - Pande, S

AU - Morgan, F

AU - Cawley, S

AU - Bruintjes, T

AU - Smit, G

AU - McGinley, B

AU - Carrillo, S

AU - Harkin, J

AU - McDaid, L

PY - 2013/10

Y1 - 2013/10

N2 - Biologically-inspired packet switched Network on Chip (NoC) basedhardware Spiking Neural Network (SNN) architectures have been proposed asan embedded computing platform for classi cation, estimation and control ap-plications. Storage of large synaptic connectivity (SNN topology) information inSNNs require large distributed on-chip memory, which poses serious challenges forcompact hardware implementation of such architectures. Based on the structuredneural organisation observed in human brain, a Modular Neural Networks (MNN)design strategy partitions complex application tasks into smaller subtasks execut-ing on distinct neural network modules, and integrates intermediate outputs inhigher level functions.This paper proposes a hardware Modular Neural Tile (MNT) architecture thatreduces the SNN topology memory requirement of NoC-based hardware SNNs byusing a combination of xed and con gurable synaptic connections. The proposedMNT contains a 16:16 fully-connected feed-forward SNN structure and integratesin a mesh topology NoC communication infrastructure. The SNN topology memoryrequirement is 50% of the monolithic NoC-based hardware SNN implementation.The paper also presents a lookup table based SNN topology memory allocationtechnique, which further increases the memory utilisation eciency. Overall thearea requirement of the architecture is reduced by an average of 66% for practicalSNN application topologies.The paper presents micro-architecture details of the proposed MNT and digitalneuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. The evolvablecapability of the proposed MNT and its suitability for executing subtasks within aMNN execution architecture is demonstrated by successfully evolving benchmarkSNN application tasks representing classi cation and non-linear control functions.The paper addresses hardware modular SNN design and implementation chal-lenges and contributes to the development of a compact hardware modular SNNarchitecture suitable for embedded applications.

AB - Biologically-inspired packet switched Network on Chip (NoC) basedhardware Spiking Neural Network (SNN) architectures have been proposed asan embedded computing platform for classi cation, estimation and control ap-plications. Storage of large synaptic connectivity (SNN topology) information inSNNs require large distributed on-chip memory, which poses serious challenges forcompact hardware implementation of such architectures. Based on the structuredneural organisation observed in human brain, a Modular Neural Networks (MNN)design strategy partitions complex application tasks into smaller subtasks execut-ing on distinct neural network modules, and integrates intermediate outputs inhigher level functions.This paper proposes a hardware Modular Neural Tile (MNT) architecture thatreduces the SNN topology memory requirement of NoC-based hardware SNNs byusing a combination of xed and con gurable synaptic connections. The proposedMNT contains a 16:16 fully-connected feed-forward SNN structure and integratesin a mesh topology NoC communication infrastructure. The SNN topology memoryrequirement is 50% of the monolithic NoC-based hardware SNN implementation.The paper also presents a lookup table based SNN topology memory allocationtechnique, which further increases the memory utilisation eciency. Overall thearea requirement of the architecture is reduced by an average of 66% for practicalSNN application topologies.The paper presents micro-architecture details of the proposed MNT and digitalneuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. The evolvablecapability of the proposed MNT and its suitability for executing subtasks within aMNN execution architecture is demonstrated by successfully evolving benchmarkSNN application tasks representing classi cation and non-linear control functions.The paper addresses hardware modular SNN design and implementation chal-lenges and contributes to the development of a compact hardware modular SNNarchitecture suitable for embedded applications.

U2 - 10.1007/s11063-012-9274-5

DO - 10.1007/s11063-012-9274-5

M3 - Article

VL - 38

SP - 131

EP - 153

JO - Neural Processing Letters

T2 - Neural Processing Letters

JF - Neural Processing Letters

SN - 1370-4621

IS - 2

ER -