Methodology for Implementing Accelerators

B Sharat Chandra Varma, Kolin Paul, M Balakrishnan

Research output: Chapter in Book/Report/Conference proceedingChapter


Many software implementation of applications have been accelerated using FPGAs. Compute intensive kernels from the application are implemented in hardware and executed in parallel to achieve speedup over softwares. FPGA consists of CLBs (consisting of LUTs and flip-flops) and interconnects which are programmable. HEBs implement performance critical components efficiently vis-a-vis their implementation using configurable logic and thus improve the performance. Adding of HEBs to FPGA fabrics may not always give performance benefits, as they occupy significant amount of chip area and sometimes may not be usable due to limitations of the memory bandwidth. A proper methodology to design HEBs and estimate the expected performance gain would be a necessary component of any design methodology. It is expected that more HEBs will be embedded into FPGAs and such a methodology will aid in building efficient reconfigurable fabrics. In this chapter, we describe a methodology to design accelerators using FPGAs with custom-designed HEBs.
Original languageUndefined
Title of host publicationArchitecture Exploration of FPGA Based Accelerators for BioInformatics Applications
Number of pages10
Publication statusPublished (in print/issue) - 3 Mar 2016


  • Memory Bandwidth
  • Call Graph
  • Hardware Accelerator
  • Application Acceleration
  • VHDL Code

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