Method for forming a semiconductor device and a semiconductor device formed by the method

CS Gormley (Inventor), A Brown (Inventor), SC Blackstone (Inventor)

Research output: Patent

Abstract

A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9). After the formation of communicating bores (30) in the lower layer (4) and thinning of the first etch stop layer (8) adjacent the micro-mirrors (10) through the communicating bores (30), openings (16) in the upper layer (6) and the micro-mirrors (10) are sequentially formed by reactive ion etching through the upper layer (6). Portions of the first and second etch stop layers (8,9) adjacent the micro-mirrors (10) are then etched away.
LanguageEnglish
Patent number09/661766
Priority date28/09/04
Publication statusPublished - 14 Sep 2000

Fingerprint

silicon
method
semiconductor
etching
annealing
insulation
thinning
spacing
oxide
damage
ion

Cite this

Gormley, CS (Inventor) ; Brown, A (Inventor) ; Blackstone, SC (Inventor). / Method for forming a semiconductor device and a semiconductor device formed by the method. Patent No.: 09/661766.
@misc{722dd1030f964ab6a1b7f42ffe8f9b66,
title = "Method for forming a semiconductor device and a semiconductor device formed by the method",
abstract = "A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9). After the formation of communicating bores (30) in the lower layer (4) and thinning of the first etch stop layer (8) adjacent the micro-mirrors (10) through the communicating bores (30), openings (16) in the upper layer (6) and the micro-mirrors (10) are sequentially formed by reactive ion etching through the upper layer (6). Portions of the first and second etch stop layers (8,9) adjacent the micro-mirrors (10) are then etched away.",
author = "CS Gormley and A Brown and SC Blackstone",
note = "Country: United States of America Commercialisation Status: assigned Patent Application Date: 2000-09-14; 09/661766",
year = "2000",
month = "9",
day = "14",
language = "English",
type = "Patent",

}

Method for forming a semiconductor device and a semiconductor device formed by the method. / Gormley, CS (Inventor); Brown, A (Inventor); Blackstone, SC (Inventor).

Patent No.: 09/661766.

Research output: Patent

TY - PAT

T1 - Method for forming a semiconductor device and a semiconductor device formed by the method

AU - Gormley, CS

AU - Brown, A

AU - Blackstone, SC

N1 - Country: United States of America Commercialisation Status: assigned Patent Application Date: 2000-09-14

PY - 2000/9/14

Y1 - 2000/9/14

N2 - A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9). After the formation of communicating bores (30) in the lower layer (4) and thinning of the first etch stop layer (8) adjacent the micro-mirrors (10) through the communicating bores (30), openings (16) in the upper layer (6) and the micro-mirrors (10) are sequentially formed by reactive ion etching through the upper layer (6). Portions of the first and second etch stop layers (8,9) adjacent the micro-mirrors (10) are then etched away.

AB - A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9). After the formation of communicating bores (30) in the lower layer (4) and thinning of the first etch stop layer (8) adjacent the micro-mirrors (10) through the communicating bores (30), openings (16) in the upper layer (6) and the micro-mirrors (10) are sequentially formed by reactive ion etching through the upper layer (6). Portions of the first and second etch stop layers (8,9) adjacent the micro-mirrors (10) are then etched away.

M3 - Patent

M1 - 09/661766

ER -