Low-power synthesis flow for regular processor design

R Woods; G Lightbody; A Cassidy; G Keane; J Spanier

doi:10.1049/ic

Low-power synthesis flow for regular processor design

R Woods
, G Lightbody
, A Cassidy
, G Keane
, J Spanier

Faculty Of Computing, Eng. & Built Env.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

153 Downloads (Pure)

Abstract

The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits for data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative "low-power" project involving the universities of Liverpool Manchester and Sheffield. The design flow is briefly described and some results are presented for multiplier implementations and their use in the development of a discrete cosine transform (DCT) circuit

Original language	English
Title of host publication	Unknown Host Publication
Publisher	Institution of Engineering and Technology
Pages	12/1 -12/5
Number of pages	5
DOIs	https://doi.org/10.1049/ic
Publication status	Published (in print/issue) - 2001
Event	IEE Seminar Low Power IC Design - London, UK, 19 Jan. 2001 Duration: 1 Jan 2001 → …

Conference

Conference	IEE Seminar Low Power IC Design
Period	1/01/01 → …

Keywords

Low power
VLSI
systolic arrays

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10.1049/ic

LowPowerSynthFlow WoodsFinal published version, 421 KB

Cite this

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title = "Low-power synthesis flow for regular processor design",

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AU - Cassidy, A

AU - Keane, G

AU - Spanier, J

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KW - Low power

KW - VLSI

KW - systolic arrays

U2 - 10.1049/ic

DO - 10.1049/ic

M3 - Conference contribution

SP - 12/1 -12/5

BT - Unknown Host Publication

PB - Institution of Engineering and Technology

T2 - IEE Seminar Low Power IC Design

Y2 - 1 January 2001

ER -

Low-power synthesis flow for regular processor design

Abstract

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Keywords

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