Low-power synthesis flow for regular processor design

R Woods, G Lightbody, A Cassidy, G Keane, J Spanier

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits for data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative "low-power" project involving the universities of Liverpool Manchester and Sheffield. The design flow is briefly described and some results are presented for multiplier implementations and their use in the development of a discrete cosine transform (DCT) circuit
LanguageEnglish
Title of host publicationUnknown Host Publication
Pages12/1 -12/5
Number of pages5
DOIs
Publication statusPublished - 2001
EventIEE Seminar Low Power IC Design - London, UK, 19 Jan. 2001
Duration: 1 Jan 2001 → …

Conference

ConferenceIEE Seminar Low Power IC Design
Period1/01/01 → …

Fingerprint

Networks (circuits)
Discrete cosine transforms
Silicon

Keywords

  • Low power
  • VLSI
  • systolic arrays

Cite this

Woods, R., Lightbody, G., Cassidy, A., Keane, G., & Spanier, J. (2001). Low-power synthesis flow for regular processor design. In Unknown Host Publication (pp. 12/1 -12/5) https://doi.org/10.1049/ic
Woods, R ; Lightbody, G ; Cassidy, A ; Keane, G ; Spanier, J. / Low-power synthesis flow for regular processor design. Unknown Host Publication. 2001. pp. 12/1 -12/5
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Woods, R, Lightbody, G, Cassidy, A, Keane, G & Spanier, J 2001, Low-power synthesis flow for regular processor design. in Unknown Host Publication. pp. 12/1 -12/5, IEE Seminar Low Power IC Design, 1/01/01. https://doi.org/10.1049/ic

Low-power synthesis flow for regular processor design. / Woods, R; Lightbody, G; Cassidy, A; Keane, G; Spanier, J.

Unknown Host Publication. 2001. p. 12/1 -12/5.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Woods R, Lightbody G, Cassidy A, Keane G, Spanier J. Low-power synthesis flow for regular processor design. In Unknown Host Publication. 2001. p. 12/1 -12/5 https://doi.org/10.1049/ic