TY - JOUR
T1 - Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks
AU - Luo, Yuling
AU - Wan, Lei
AU - Liu, Junxiu
AU - Harkin, Jim
AU - McDaid, LJ
AU - Cao, Yi
AU - Ding, Xuemei
PY - 2018/11/21
Y1 - 2018/11/21
N2 - A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs.
AB - A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs.
KW - interconnected architecture
KW - Spiking Neural Networks
KW - Networks-on-Chip
KW - system scalability
KW - arbitration scheme
UR - https://pure.ulster.ac.uk/en/publications/low-cost-interconnected-architecture-for-the-hardware-spiking-neu
U2 - 10.3389/fnins.2018.00857
DO - 10.3389/fnins.2018.00857
M3 - Article
C2 - 30524230
SN - 1662-453X
VL - 12
SP - 1
EP - 14
JO - Frontiers in Neurosciences
JF - Frontiers in Neurosciences
M1 - 857
ER -