Linear QR Architecture for a Single Chip Adaptive Beamformer

G Lightbody, R Walke, R Woods, J McCanny

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
LanguageEnglish
Pages67-81
JournalThe Journal of VLSI Signal Processing
Volume24
Issue number1
DOIs
Publication statusPublished - 2000

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Networks (circuits)
Intellectual property core

Keywords

  • VLSI
  • systolic arrays
  • QR
  • RLS
  • mapping

Cite this

Lightbody, G ; Walke, R ; Woods, R ; McCanny, J. / Linear QR Architecture for a Single Chip Adaptive Beamformer. In: The Journal of VLSI Signal Processing. 2000 ; Vol. 24, No. 1. pp. 67-81.
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abstract = "This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.",
keywords = "VLSI, systolic arrays, QR, RLS, mapping",
author = "G Lightbody and R Walke and R Woods and J McCanny",
note = "Reference text: 1. L.C. Godara, “Application of antenna arrays to mobile communications, Part II: Beam-forming and direction-of-arrival considerations,” Proc. of the IEEE, Vol. 85, No. 8, pp. 1195–1245, 1997. 2. T.J. Shephard and J.G. McWhirter, “Systolic adaptive beamforming,” chap. 5, Array Processing, S. Haykin, J. Litva, and T.J. Shephard (Eds.), Springer-Verlag, ISBN 3-540-55224, 1993, pp. 153–243. 3. C.M. Rader, “VLSI systolic arrays for adaptive nulling,” IEEE Signal Processing Magazine, Vol. 13, No. 4, 1996, pp. 29–49. 4. C.M. Rader, “MUSE: A systolic array for adaptive nulling with 64 degrees of freedom using givens transformations and wafer scale integration,” Proc. of the Int. Conf. of Application Specific Array Processors, pp. 277–291, 1992. 5. Kalouptsidis and Theodoridis, Adaptive System Identification and Signal Processing Algorithms, Englewood Cliffs, NJ: Prentice Hall, 1993. 6. S. Haykin, Adaptive Filter Theory, Englewood Cliffs, NJ: Prentice Hall, 1986. 7. J.M. Cioffi and T. Kailath, “Fast recursive-least-square, transversal filters for adaptive filtering,” IEEE Trans. Acoustics, Speech, Signal Processing, Vol. ASSP-32, No. 2, pp. 998–1005, 1984. 8. R.L. Walke, “High sample rate givens rotations for recursive least squares,” Ph.D. Thesis, University of Warwick, 1997. 9. W. Givens, “Computation of plane unitary rotations transforming a general matrix to triangular form,” J. Soc. Ind. Appl. Math, Vol. 6, pp. 26–50. 10. W.M. Gentleman and H.T. Kung, “Matrix triangularisation by systolic array,” Proc. SPIE (Real-Time Signal Processing IV), pp. 329–369, 1973. 11. J.G. McWhirter, “Recursive least squares minimisation using systolic array,” Proc. SPIE (Real-Time Signal Processing IV), Vol. 431, pp. 105–112, 1983. 12. S.F. Hsieh, K.J.R. Liu, and K.Yao, “Aunified approach for QRD based recursive least-squares estimation without square roots,” IEEE Trans. On Signal Processing, Vol. 41, No. 3, pp. 1405– 1409, 1993. 13. R. D¨ohler, “Squared given’s rotations,” IMA J. of Numerical Analysis, Vol. II, pp. 1–5, 1991. 14. J.G. McWhirter, R.L.Walke, and J. Kadlec, “Normalised givens rotations for recursive least squares processing,” VLSI Signal Processing, VIII, .ISBN 0-7803-2612-1, pp. 323–332, 1995. 15. G. Lightbody, R. Walke, R. Woods, and J. McCanny, “Rapid design of a single chip adaptive beamformer,” IEEE Proc. on Signal Processing Systems, pp. 285–294, 1998. 16. S.Y. Kung, VLSI Array Processors, Englewood Cliffs, New Jersey: Prentice Hall, 1988. 17. A.S. Coffey, M. Johnson, and R. Jones, “Nonlinear dynamical systems analyser,” Proc. SPIE 2296, pp. 687–699, 1996. 18. J.V. McCanny, D. Ridge, Y. Hu, and J. Hunter, “Hierarchical VHDL libraries for DSP ASIC design,” ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing, proceedings, 1997, Vol. 1, pp. 675–678. 19. D.W. Trainor “An architectural synthesis tool for VLSI signal processing chips,” Ph.D. Thesis, Queen’s University of Belfast, 1995. 20. D.W. Trainor, R.F. Woods, and J.V. McCanny, “Architectural synthesis of digital signal processing algorithms using ‘IRIS’,” Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Vol. 16, No. 1, pp. 41–55, 1997. 21. J. Litva and T.K. Lo, Digital Beamforming in Wireless Communications, Artech House Publishers, 1996. 22. X. Messtre, M. N´ajar, and M. Lagunas, “Two-stage code reference beamformer in mobile communication,” ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing, proceedings, Vol. 6, pp. 3309–3312, 1998. 23. T.J. Shephard and J.G. McWhirter, “Systolic adaptive beamforming,” chap. 5, Array Processing, S. Haykin, J. Litva, and T.J. Shephard (Eds.), Springer-Verlag, ISBN 3-540-55224, 1993, pp. 153–243. 24. A. Wenzler and E. Lueder, “New structures for complex multipliers and their noise analysis,” Proc. IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1432–1435, 1995. 25. M. Renfors and Y. Neuvo, “The maximum sample rate of digital filters under hardware speed constraints,” IEEE Transactions on Circuits and Systems, Vol. CAS-28, No. 3, pp. 196–202, 1981. 26. R. Woods, “High performance VLSI architectures for recursive filtering,” Ph.D. Thesis, Queen’s University of Belfast, 1990.",
year = "2000",
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language = "English",
volume = "24",
pages = "67--81",
journal = "The Journal of VLSI Signal Processing",
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}

Linear QR Architecture for a Single Chip Adaptive Beamformer. / Lightbody, G; Walke, R; Woods, R; McCanny, J.

In: The Journal of VLSI Signal Processing, Vol. 24, No. 1, 2000, p. 67-81.

Research output: Contribution to journalArticle

TY - JOUR

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AU - Lightbody, G

AU - Walke, R

AU - Woods, R

AU - McCanny, J

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PY - 2000

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N2 - This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

AB - This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

KW - VLSI

KW - systolic arrays

KW - QR

KW - RLS

KW - mapping

U2 - 10.1023/A:1008118711904

DO - 10.1023/A:1008118711904

M3 - Article

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EP - 81

JO - The Journal of VLSI Signal Processing

T2 - The Journal of VLSI Signal Processing

JF - The Journal of VLSI Signal Processing

SN - 1573-109X

IS - 1

ER -