@article{8eb5a86f8cf747ea9ecd97541e33fabb,

title = "Linear QR Architecture for a Single Chip Adaptive Beamformer",

abstract = "This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.",

keywords = "VLSI, systolic arrays, QR, RLS, mapping",

author = "G Lightbody and R Walke and R Woods and J McCanny",

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year = "2000",

doi = "10.1023/A:1008118711904",

language = "English",

volume = "24",

pages = "67--81",

journal = "The Journal of VLSI Signal Processing",

issn = "1573-109X",

publisher = "Springer",

number = "1",

}