This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
- systolic arrays
Lightbody, G., Walke, R., Woods, R., & McCanny, J. (2000). Linear QR Architecture for a Single Chip Adaptive Beamformer. The Journal of VLSI Signal Processing, 24(1), 67-81. https://doi.org/10.1023/A:1008118711904