Layered tile architecture for efficient hardware spiking neural networks

Lei Wan, Junxiu Liu, Jim Harkin, Liam McDaid, Yuling Lou

Research output: Contribution to journalArticle

Abstract

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviour of biological neuron system. However, its main drawback is that it is computationally intensive, which limits the system scalability. This paper highlights and discusses the importance and significance of emulating SNNs in hardware devices. A layer-level tile architecture (LTA) is proposed for hardware-based SNNs. The LTA employs a two-level sharing mechanism of computing components at the synapse and neuron levels, and achieves a trade-off between computational complexity and hardware resource costs. The LTA is implemented on a Xilinx FPGA device. Experimental results demonstrate that this approach is capable of scaling to large hardware-based SNNs.
LanguageEnglish
Pages21-32
JournalMicroprocessors and Microsystems
Volume53
Early online date8 Jul 2017
DOIs
Publication statusPublished - Aug 2017

Fingerprint

Tile
Neural networks
Hardware
Neurons
Field programmable gate arrays (FPGA)
Scalability
Computational complexity
Costs

Keywords

  • Spiking neural networks
  • Networks on Chip
  • Layer-level tile architecture
  • FPGAs
  • Sharing mechanism

Cite this

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Layered tile architecture for efficient hardware spiking neural networks. / Wan, Lei; Liu, Junxiu; Harkin, Jim; McDaid, Liam; Lou, Yuling.

Vol. 53, 08.2017, p. 21-32.

Research output: Contribution to journalArticle

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