Investigation of Programmable Threshold Logic Gate Array

Peter Kelly, C.J. Thompson, TM McGinnity, Liam Maguire

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Citations (Scopus)


A study of simulated InP-based RTD/HFET threshold logic gates (TLGs), deployed in an array suited to the implementation of programmable neural network-like architectures, is carried out. A new programmable TLG and an EX-OR TLG are presented. An array of programmable and non-programmable TLGs is studied to demonstrate an application with field programmability and to determine the suitability of the technology for the realisation of these gates in larger scale integrated circuits. The architecture may have the potential for a flexible platform that will allow training and reconfiguration of a cellular artificial neural network (ANN). The functionality of the circuit architecture is investigated and the effects of variations in device-characteristics, and clocked power supply on its operation are considered to assess the potential use of TLG circuits in the context of larger scale implementations.
Original languageEnglish
Title of host publicationUnknown Host Publication
Number of pages4
Publication statusPublished (in print/issue) - Jan 2002
EventIEEE 9th International Conference on Electronics, Circuits and Systems, 2002. -
Duration: 1 Jan 2002 → …


ConferenceIEEE 9th International Conference on Electronics, Circuits and Systems, 2002.
Period1/01/02 → …


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