|Title of host publication||Unknown Host Publication|
|Number of pages||6|
|Publication status||Published - 2006|
|Event||IEEE International Joint Conference on Neural Networks - Vacouver, Canada|
Duration: 1 Jan 2006 → …
|Conference||IEEE International Joint Conference on Neural Networks|
|Period||1/01/06 → …|
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Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling. / Tuffy, F; McDaid, LJ; Kwan, VW; Alderman, J; McGinnity, TM; Kelly, PM; Santos, JA.Unknown Host Publication. IEEE, 2006. p. 2779-2784.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
TY - GEN
T1 - Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling
AU - Tuffy, F
AU - McDaid, LJ
AU - Kwan, VW
AU - Alderman, J
AU - McGinnity, TM
AU - Kelly, PM
AU - Santos, JA
N1 - Reference text:  B. Roche, T. M. McGinnity, L. P. Maguire, L. J. McDaid, “Signalling Techniques and their Effect on Neural Network Implementation Sizes,” Information Sciences 132, pages 67-82, NH Elsevier, 2001  A. F. Murray and R. Woodburn, “The Prospects for Analogue Neural VLSI, International Journal of Neural Systems,” Vol. 8, No. 5 & 6, pages 559-579, Oct/Dec. 1997  S. C. Liu, J. Kramer, G. Indiveri, T. Delbruck, T. Burg, and R. Douglas, “Orientation-selective a VLSI spiking neurons,” Neural Networks, Special Issue on Spiking Neurons in Neuroscience and Technology , Vol. 14, Issues 6-7, pages 629-643, July 2001  C. Diorio, D. Hsu and M. Figueroa, “Adaptive CMOS: from biological inspiration to systems-on-a-chip,” Proceedings of the IEEE, Vol. 90, Issue 3, pages 345 – 357, March 2002  D. H. Goldberg, G. Cauwenberghs, A. G. Andreou, “Probabilistic synaptic weighting in a reconfigurable network of VLSI integrateand-fire neurons,” Neural Networks, Vol. 14, no. 6–7, pages 781–793, Sept 2001  W. Maass, Computation with Spiking Neurons: the Handbook of Brain Theory and Neural Networks, MIT Press, 1998.  B. Noory, V. Groza, “A reconfigurable approach to hardware implementation of neural networks,” IEEE CCECE 2003. Canadian Conference on Electrical and Computer Engineering, pages 1861 - 1864 Vol. 3, 4-7 May 2003  L. Chun, B. Shi; L. Chen, “Hardware implementation of an expandable on-chip learning neural network with 8-neuron and 64-synapse,” TENCON '02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, Vol. 3, pages 1451 – 1454, 28-31 Oct. 2002  T. Miki, Editor, Brainware:Bio-Inspired Architectures and its Hardware Implementation, World Scientific Publishing Co. Ltd, 2001.  J. Schemmel, S. Hohmann, K. Meier and F. Schürmann, “A MixedMode Analog Neural Network Using Current-Steering Synapses,” Analog Integrated Circuits and Signal Processing, Vol. 38, Numbers 2-3 , pages 233 – 244, February 2004  R. H. Havemann and J. A. Hutchby, “High-Performance Interconnects: An Integration Overview,” Proceedings of the IEEE, Vol. 89, No.5, May 2001  J. J. Rosato, SCP Global Technologies, “Critical Cleaning Challenges for Copper / Low-k Interconnect Systems,” Future Fab Intl. Vol. 8, http://www.future-fab.com  J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, J. D. Meindl, “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,” Proceedings of the IEEE, Vol. 89, Issue: 3, pages 305 – 324, March 2001.  J. D. Meindl, R. Venkatesan, J. A.Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. A. Kohl, K. P. Martin, “Interconnecting Device Opportunities for Gigascale Integration (GSI),” 2001 IEDM International Technical Digest Electron Devices Meeting, pages 23.1.1-23.1.4.  J. W. Joyner, P. Zarkesh-Ha, J. D. Meindl, “Global Interconnect Design in a Three-Dimensional System-on-a-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, Issue: 4, pages 367 – 372, April 2004.  M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. N. Glytsis, J. D. Meindl, “Optical Transmission of Polymer Pillars for Chip I/O Optical Interconnects,” IEEE Photonics Technology Letters, Vol. 16, Issue: 1, pages 117 – 119, Jan. 2004  P. Wang, G. Pei and E. C-C. Kan, “Pulsed wave Interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12, No.5, May 2004  T. P. Trappenberg, Fundamentals of Computational Neuroscience, Oxford University Press, June, 2002  K. C. Smith, “Multiple-Valued Logic: A Tutorial and Appreciation,” IEEE Computer 1998, Vol. 21, Issue: 4, pages 17 – 27, April 1988  K. D. Maier, C. Beckstein, R. Blickhan, W. Erhard, D. Fey, “A multi-layer-perceptron neural network hardware based on 3D massively parallel optoelectronic circuits,” Proceedings of the 6th International Conference on Parallel Interconnects, 1999. (PI '99), Page(s):73 – 80, 17-19 Oct. 1999  D. A. B. Miller, “Rationale and Challenges for Optical Interconnects to Electronic Chips,” Proceedings of the IEEE, Vol. 88, Issue: 6, pages 728 – 749, June 2000.  B. A. Floyd, X. Guo, J. Caserta, T. Dickson, C.M. Hung, K. Kim and K. K. O, “Wireless Interconnects for clock distribution,” Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pages 105-108, 02 - 03 Dec. 2002  M. F. Chang, V. P. Roychowdhury, L. Zhang, H. Shin and Y. Qian, “RF / Wireless Interconnect for Inter and Intra Chip Communications,” Proceedings of the IEEE, Vol. 89, No.4, April 2001  S. Mick, L. Luo, J. Wilson, P. Franzon, “Buried Bump and AC Coupled Interconnection Technology,” IEEE Transactions on Advanced Packaging, Vol. 27 , Issue: 1 , pages 121 – 125, Feb. 2004  E. Chicca, D. Badoni, V. Dante, M. D’Andreagiovanni, G. Salina, L. Carota, S. Fusi and P. Del Giudice, “A VLSI recurrent network of integrate and fire neurons connected by plastic synapses with long term memory”, IEEE Trans. on Neural Networks,Vol.14, No.5, Sept. 2003  C. T.-C Nguyen and R. T. Howe, “An integrated CMOS micromechanical resonator high-Q oscillator,” IEEE Journal SolidState Circuits, vol.34, No. 4, 1999  P. J. Hughes, B. O’Neill, J. F. Rohan, M. Hill, D. Berneck, C. O’Mahony, J. O’Brien, and W. A. Lane. “Memswitch: CMOS compatible surface micromachined switches & relays,” The Eleventh MicroMechanics Europe Workshop, MME'00, Uppsala, Sweden., 1-3 October 2000.  Z. Olszewski, M. Hill, C. O'Mahony, and R. Duane, “Characterisation, modelling and performance evaluation of CMOS integrated Multielectrode Tunable Capacitor (MTC),” Journal of Micromechanics and Microengineering, 15, pages S122-S131, 2005.  C. O'Mahony, R. Duane, M. Hill, and A. Mathewson, “A Long Lifetime, Low Voltage, Capacitive RF Microswitch,” Proceedings of the 15th Micromechanics Europe, Leuven, Belgium, pages 237-240, 5-7th September 2004.  J. R. Clark, F. D. Bannon III, W. Ark-Chew, and C. T.-C. Nguyen, "Parallel-Resonator HF Micromechanical Bandpass Filters," Proceedings of the Conference on Solid State Sensors and Actuators: Transducers '97, Chicago, Illinois, Vol. 2, 1997, pages 1161-1164.  F. D. Bannon III, J. R. Clark, and C. T.-C. Nguyen, "High Frequency Microelectromechanical IF Filters," IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 8-11, 1996, pages 773-776.  K. Wang, Y. Yu, A.-C. Wong, and C. T.-C. Nguyen, “VHF FreeFree Beam High-Q Micromechanical Resonators,” 12th International IEEE Micro Electro Mechanical Systems Conference, Orlando, Florida, Jan. 17-21, 1999, pages 453-458.  J. Wang, Y. Xie, and C. T.-C. Nguyen, “Frequency Tolerance of RF Micromechanical Disk Resonators in Nanocrystalline Diamond and Polysilicon Structural Materials,” IEEE International Electron Devices Meeting, Washington, DC, Dec. 5-7, 2005, pages 291-294.
PY - 2006
Y1 - 2006
N2 - A novel inter-neuron communications method for increased scalability of Spiking Neural Networks (SNNs) is presented. Capacitive coupling is used as the communication medium with spike functions replaced by oscillatory bursts. The dependency of the coupling signals between neuron layers as a function of neuron density, frequency and track loading is predicted. High Q decoding filters and accurate frequency matching between transmitting neurons and receiving synapses was achieved using band pass filters. Micro-ElectroMechanical Systems (MEMS) were used in the filter circuits and burst oscillators because of their high Q values. The method of fabricating the on-chip coupling capacitors and associated oscillator/filter circuits is discussed.
AB - A novel inter-neuron communications method for increased scalability of Spiking Neural Networks (SNNs) is presented. Capacitive coupling is used as the communication medium with spike functions replaced by oscillatory bursts. The dependency of the coupling signals between neuron layers as a function of neuron density, frequency and track loading is predicted. High Q decoding filters and accurate frequency matching between transmitting neurons and receiving synapses was achieved using band pass filters. Micro-ElectroMechanical Systems (MEMS) were used in the filter circuits and burst oscillators because of their high Q values. The method of fabricating the on-chip coupling capacitors and associated oscillator/filter circuits is discussed.
U2 - 10.1109/IJCNN.2006.247184
DO - 10.1109/IJCNN.2006.247184
M3 - Conference contribution
SP - 2779
EP - 2784
BT - Unknown Host Publication
PB - IEEE
T2 - IEEE International Joint Conference on Neural Networks
Y2 - 1 January 2006