Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this work, we propose a novel plastic neural network model which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory inter neurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA.The system is able to maintain stable firing with a loss of up to 75% of the original synaptic inputs to a neuron.Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only 3 slices/neuron for implementing a threshold voltage based homeostatic fault tolerant unit. The overall architecture has a minimal impact on power consumption and therefore supports scalable implementations.This work opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Early online date||28 Jul 2017|
|Publication status||Published - Feb 2018|
- Fault Tolerance
- Dynamic Partial Reconfiguration
- Bio-inspired Engineering
- Mode Clock Manager
- Phase Locked loop.
Johnson, A., Liu, J., Millard, A., Karim, S., Tyrrell, A., Harkin, J., Timmis, J., McDaid, L., & Halliday, D. (2018). Homeostatic Fault Tolerance in Spiking NeuralNetworks: A Dynamic Hardware Perspective. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(2), 687-699. https://doi.org/10.1109/TCSI.2017.2726763