Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

A. P. Johnson, Junxiu Liu, A. G. Millard, S. Karim, A. M. Tyrrell, Jim Harkin, J. Timmis, Liam McDaid, D. M. Halliday

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90 of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215 of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.
LanguageEnglish
Title of host publicationUnknown Host Publication
Pages195-198
Number of pages4
DOIs
Publication statusAccepted/In press - 15 Sep 2017
Event2017 International Conference on Field Programmable Technology (ICFPT) -
Duration: 15 Sep 2017 → …

Conference

Conference2017 International Conference on Field Programmable Technology (ICFPT)
Period15/09/17 → …

Fingerprint

Fault tolerance
Field programmable gate arrays (FPGA)
Repair
Neurons
Neural networks
Clocks
Hardware
Recovery
Tile
Brain
Electric power utilization
Astrocytes

Keywords

  • Circuit faults
  • Clocks
  • Fault tolerance
  • Field programmable gate arrays
  • Hardware
  • Neurons
  • Synapses
  • neural networks
  • astrocyte

Cite this

Johnson, A. P., Liu, J., Millard, A. G., Karim, S., Tyrrell, A. M., Harkin, J., ... Halliday, D. M. (Accepted/In press). Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs. In Unknown Host Publication (pp. 195-198) https://doi.org/10.1109/FPT.2017.8280139
Johnson, A. P. ; Liu, Junxiu ; Millard, A. G. ; Karim, S. ; Tyrrell, A. M. ; Harkin, Jim ; Timmis, J. ; McDaid, Liam ; Halliday, D. M. / Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs. Unknown Host Publication. 2017. pp. 195-198
@inproceedings{8b888c8a9f3545f597e6883dff329f16,
title = "Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs",
abstract = "We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90 of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215 of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.",
keywords = "Circuit faults, Clocks, Fault tolerance, Field programmable gate arrays, Hardware, Neurons, Synapses, neural networks, astrocyte",
author = "Johnson, {A. P.} and Junxiu Liu and Millard, {A. G.} and S. Karim and Tyrrell, {A. M.} and Jim Harkin and J. Timmis and Liam McDaid and Halliday, {D. M.}",
year = "2017",
month = "9",
day = "15",
doi = "10.1109/FPT.2017.8280139",
language = "English",
pages = "195--198",
booktitle = "Unknown Host Publication",

}

Johnson, AP, Liu, J, Millard, AG, Karim, S, Tyrrell, AM, Harkin, J, Timmis, J, McDaid, L & Halliday, DM 2017, Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs. in Unknown Host Publication. pp. 195-198, 2017 International Conference on Field Programmable Technology (ICFPT), 15/09/17. https://doi.org/10.1109/FPT.2017.8280139

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs. / Johnson, A. P.; Liu, Junxiu; Millard, A. G.; Karim, S.; Tyrrell, A. M.; Harkin, Jim; Timmis, J.; McDaid, Liam; Halliday, D. M.

Unknown Host Publication. 2017. p. 195-198.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

AU - Johnson, A. P.

AU - Liu, Junxiu

AU - Millard, A. G.

AU - Karim, S.

AU - Tyrrell, A. M.

AU - Harkin, Jim

AU - Timmis, J.

AU - McDaid, Liam

AU - Halliday, D. M.

PY - 2017/9/15

Y1 - 2017/9/15

N2 - We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90 of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215 of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

AB - We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90 of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215 of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

KW - Circuit faults

KW - Clocks

KW - Fault tolerance

KW - Field programmable gate arrays

KW - Hardware

KW - Neurons

KW - Synapses

KW - neural networks

KW - astrocyte

U2 - 10.1109/FPT.2017.8280139

DO - 10.1109/FPT.2017.8280139

M3 - Conference contribution

SP - 195

EP - 198

BT - Unknown Host Publication

ER -