Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90 of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215 of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.