Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Anju Johnson, Junxiu Liu, Alan Millard, Shvan Karim, Andy Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David Halliday

Research output: Contribution to journalArticlepeer-review

32 Citations (Scopus)
70 Downloads (Pure)


Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this work, we propose a novel plastic neural network model which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory inter neurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA.The system is able to maintain stable firing with a loss of up to 75% of the original synaptic inputs to a neuron.Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only 3 slices/neuron for implementing a threshold voltage based homeostatic fault tolerant unit. The overall architecture has a minimal impact on power consumption and therefore supports scalable implementations.This work opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.
Original languageEnglish
Pages (from-to)687-699
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number2
Early online date28 Jul 2017
Publication statusPublished (in print/issue) - 25 Jan 2018


  • Self-Repair
  • Homeostasis
  • Fault Tolerance
  • FPGA
  • Dynamic Partial Reconfiguration
  • Bio-inspired Engineering
  • Mixed-
  • Mode Clock Manager
  • Phase Locked loop.


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