Abstract
Many scientific applications take a very long time to execute on general purpose processors. Speedups can be obtained by using specialized hardware in conjunction with the processors. FPGA based accelerators are known to be effective for reducing the execution time of many scientific applications. Since FPGAs are configurable, they can be customized to implement a variety of processing elements as accelerators. The process of mapping algorithm to architecture is complex, as the design space is large. System simulation is usually employed to carry out the exploration, in spite of the fact that simulation models take significantly large amount of time to execute. High level design space exploration helps in taking the required decisions to arrive at an optimal design. In this paper we describe design space exploration carried out for accelerating de novo genome assembly using FPGAs. Three models at various levels of abstraction were used. We discuss how the simulation time of these models influence the choice of design parameters at different levels of abstraction. We illustrate this process by using the high level models to evaluate Hard Embedded Blocks (HEBs) in FPGAs for accelerating the de novo genome assembly application.
Original language | English |
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Title of host publication | 2014 17th Euromicro Conference on Digital System Design |
Publisher | IEEE Xplore |
Pages | 66-73 |
Number of pages | 8 |
DOIs | |
Publication status | Published (in print/issue) - 1 Aug 2014 |
Keywords
- field programmable gate arrays
- high level synthesis
- logic design
- FPGA based accelerator
- HEB
- de novo genome assembly
- design parameter
- general purpose processor
- hard embedded block
- high level design approach
- high level design space exploration
- high level model
- mapping algorithm
- processing element
- simulation time
- specialized hardware
- system simulation
- Acceleration
- Assembly
- Bioinformatics
- Field programmable gate arrays
- Genomics
- Hardware
- Space exploration
- FPGA based acceleration
- Genome assembly
- Hard embedded blocks
- System level simulation