Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Scalable hardware interconnect is a significant research challenge for neuromorphic systems in particular, this becomes more pronounced when we seek to realise the integration of neurons with astrocytes cells. This paper pre-sents a novel interactive architecture for the astrocyte-neuron network (ANN) hardware systems, and the novel Hierarchical Astrocyte Network Architecture (HANA) using networks-on-chip (NoC) for the efficient information exchange between astrocyte cells. The proposed HANA incorporates a two-level NoC packet transmission mechanism to increase the information exchange rate be-tween astrocyte cells and to provide a NoC traffic balance for local and global astrocyte networks. Experimental results demonstrate that the proposed HANA approach can provide efficient information exchange rates for the ANN, while the hardware synthesis results using 90nm CMOS technology show that it has a low area overhead which maintains scalability.
LanguageEnglish
Title of host publicationUnknown Host Publication
Number of pages8
DOIs
Publication statusAccepted/In press - 12 Jun 2016
Event25th International Conference on Artificial Neural Networks -
Duration: 12 Jun 2016 → …

Conference

Conference25th International Conference on Artificial Neural Networks
Period12/06/16 → …

Fingerprint

Neurons
Hardware
Network architecture
Network-on-chip
Astrocytes
Computer hardware
Scalability
Computer systems

Keywords

  • Astrocyte-neuron network
  • networks-on-chip
  • interconnect
  • self-repair
  • FPGAs

Cite this

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title = "Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware",
abstract = "Scalable hardware interconnect is a significant research challenge for neuromorphic systems in particular, this becomes more pronounced when we seek to realise the integration of neurons with astrocytes cells. This paper pre-sents a novel interactive architecture for the astrocyte-neuron network (ANN) hardware systems, and the novel Hierarchical Astrocyte Network Architecture (HANA) using networks-on-chip (NoC) for the efficient information exchange between astrocyte cells. The proposed HANA incorporates a two-level NoC packet transmission mechanism to increase the information exchange rate be-tween astrocyte cells and to provide a NoC traffic balance for local and global astrocyte networks. Experimental results demonstrate that the proposed HANA approach can provide efficient information exchange rates for the ANN, while the hardware synthesis results using 90nm CMOS technology show that it has a low area overhead which maintains scalability.",
keywords = "Astrocyte-neuron network, networks-on-chip, interconnect, self-repair, FPGAs",
author = "J Liu and J Harkin and LJ McDaid and G Martin",
year = "2016",
month = "6",
day = "12",
doi = "10.1007/978-3-319-44778-0",
language = "English",
booktitle = "Unknown Host Publication",

}

Liu, J, Harkin, J, McDaid, LJ & Martin, G 2016, Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware. in Unknown Host Publication. 25th International Conference on Artificial Neural Networks, 12/06/16. https://doi.org/10.1007/978-3-319-44778-0

Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware. / Liu, J; Harkin, J; McDaid, LJ; Martin, G.

Unknown Host Publication. 2016.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Scalable hardware interconnect is a significant research challenge for neuromorphic systems in particular, this becomes more pronounced when we seek to realise the integration of neurons with astrocytes cells. This paper pre-sents a novel interactive architecture for the astrocyte-neuron network (ANN) hardware systems, and the novel Hierarchical Astrocyte Network Architecture (HANA) using networks-on-chip (NoC) for the efficient information exchange between astrocyte cells. The proposed HANA incorporates a two-level NoC packet transmission mechanism to increase the information exchange rate be-tween astrocyte cells and to provide a NoC traffic balance for local and global astrocyte networks. Experimental results demonstrate that the proposed HANA approach can provide efficient information exchange rates for the ANN, while the hardware synthesis results using 90nm CMOS technology show that it has a low area overhead which maintains scalability.

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