Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware

S Carrillo; Jim Harkin; Liam McDaid

doi:10.1007/978-3-662-44616-4_12

Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware

S Carrillo
, Jim Harkin
, Liam McDaid

VCRS

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Original language	English
Title of host publication	Natural Computing Series, Special Topic - Evolvable Hardware
Publisher	Springer
Pages	297-330
ISBN (Print)	978-3-662-44615-7
DOIs	https://doi.org/10.1007/978-3-662-44616-4_12
Publication status	Published (in print/issue) - 15 Sept 2015

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Keywords

Networks-on-chip
spiking neural networks
FPGA
neuromorphic
hardware acceleration

Access to Document

10.1007/978-3-662-44616-4_12

Cite this

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title = "Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware",

keywords = "Networks-on-chip, spiking neural networks, FPGA, neuromorphic, hardware acceleration",

author = "S Carrillo and Jim Harkin and Liam McDaid",

year = "2015",

month = sep,

day = "15",

doi = "10.1007/978-3-662-44616-4\_12",

language = "English",

isbn = "978-3-662-44615-7",

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T1 - Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware

AU - Carrillo, S

AU - Harkin, Jim

AU - McDaid, Liam

PY - 2015/9/15

Y1 - 2015/9/15

KW - Networks-on-chip

KW - spiking neural networks

KW - FPGA

KW - neuromorphic

KW - hardware acceleration

U2 - 10.1007/978-3-662-44616-4_12

DO - 10.1007/978-3-662-44616-4_12

M3 - Chapter

SN - 978-3-662-44615-7

SP - 297

EP - 330

BT - Natural Computing Series, Special Topic - Evolvable Hardware

PB - Springer

ER -