Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations

S Carrillo, JG Harkin, LJ McDaid, S Pande, S Cawley, B McGinley, F Morgan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

19 Citations (Scopus)


The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.
Original languageEnglish
Title of host publicationUnknown Host Publication
Number of pages8
Publication statusPublished (in print/issue) - 9 May 2012
EventACM/IEEE International Symposium on Networks-on-Chip (NoC) - Denmark
Duration: 9 May 2012 → …


ConferenceACM/IEEE International Symposium on Networks-on-Chip (NoC)
Period9/05/12 → …


  • Network-on-Chip
  • Traffic Compression
  • Spiking Neural Network
  • hardware


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