Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations

S Carrillo, JG Harkin, LJ McDaid, S Pande, S Cawley, B McGinley, F Morgan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.
LanguageEnglish
Title of host publicationUnknown Host Publication
Number of pages8
Publication statusPublished - 9 May 2012
EventACM/IEEE International Symposium on Networks-on-Chip (NoC) - Denmark
Duration: 9 May 2012 → …

Conference

ConferenceACM/IEEE International Symposium on Networks-on-Chip (NoC)
Period9/05/12 → …

Fingerprint

Neurons
Neural networks
Throughput
Hardware
Routers
Scalability
Electric power utilization
Topology
Network-on-chip
Costs

Keywords

  • Network-on-Chip
  • Traffic Compression
  • Spiking Neural Network
  • hardware

Cite this

Carrillo, S., Harkin, JG., McDaid, LJ., Pande, S., Cawley, S., McGinley, B., & Morgan, F. (2012). Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. In Unknown Host Publication
Carrillo, S ; Harkin, JG ; McDaid, LJ ; Pande, S ; Cawley, S ; McGinley, B ; Morgan, F. / Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. Unknown Host Publication. 2012.
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abstract = "The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.",
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Carrillo, S, Harkin, JG, McDaid, LJ, Pande, S, Cawley, S, McGinley, B & Morgan, F 2012, Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. in Unknown Host Publication. ACM/IEEE International Symposium on Networks-on-Chip (NoC), 9/05/12.

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. / Carrillo, S; Harkin, JG; McDaid, LJ; Pande, S; Cawley, S; McGinley, B; Morgan, F.

Unknown Host Publication. 2012.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Carrillo, S

AU - Harkin, JG

AU - McDaid, LJ

AU - Pande, S

AU - Cawley, S

AU - McGinley, B

AU - Morgan, F

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N2 - The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

AB - The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware, which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33x109 spikes/second), and synthesis results using 65-nm CMOS demonstrate low cost area (0.58mm2) and power consumption (13.16mW @ 100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

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Carrillo S, Harkin JG, McDaid LJ, Pande S, Cawley S, McGinley B et al. Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. In Unknown Host Publication. 2012