Abstract
..Elliptic Curve Cryptography (ECC) is the front-runner among available public key cryptography (PKC) schemes due to its potential to offer higher security per key bit. All ECC-based cryptosystems heavily rely on point multiplication operation where its efficient realization has attained notable focus in the research community. Low latency implementation of the point multiplication operation is frequently required in high-speed applications such as online authentication and web server certification. This paper presents a low latency ECC point multiplication architecture for Montgomery curves over generic prime field GF(p). The proposed architecture is able to operate for a general prime modulus without any constraints on its structure. It is based on a new novel pipelined modular multiplier developed using the Montgomery multiplication and the Karatsuba-Offman technique with a four-part splitting methodology. The Montgomery ladder approach is adopted on a system level, where a high-speed scheduling strategy to efficiently execute GF(p) operations is also presented. Due to these circuit and system-level optimizations, the proposed design delivers low-latency results without a significant increase in resource consumption. The proposed architecture is described in Verilog-HDL for 256-bit key lengths and implemented on Virtex-7 and Virtex-6 FPGA platforms using Xilinx ISE Design Suite. On the Virtex-7 FPGA platform, it performs a 256-bit point multiplication operation in just 110.9 us with a throughput of almost 9017 operations per second. The implementation results demonstrate that despite its generic nature, it produces low latency as compared to the state-of-the-art. Therefore, it has prominent prospects to be used in high-speed authentication and certification applications.
| Original language | English |
|---|---|
| Article number | 104946 |
| Pages (from-to) | 1-11 |
| Number of pages | 11 |
| Journal | Journal of Parallel and Distributed Computing |
| Volume | 193 |
| Early online date | 3 Jul 2024 |
| DOIs | |
| Publication status | Published (in print/issue) - 30 Nov 2024 |
Bibliographical note
Publisher Copyright:© 2024 Elsevier Inc.
Funding
This work was supported, in part, by Science Foundation Ireland under Grant No. and, in part, by the European Union's Horizon 2020 research and innovation program under the Marie Sk\u0142odowska-Curie grant agreement and Grant No. 754489 This work was supported, in part, by Science Foundation Ireland under Grant No. 13/RC/2094-P2 and, in part, by the European Union's Horizon 2020 research and innovation program under the Marie Sk\u0142odowska-Curie grant agreement and Grant No. 754489
| Funders | Funder number |
|---|---|
| European Union's Horizon Europe research and innovation programme | |
| European Union Horizon 2020 Marie Skłodowska-Curie Fellowship | 754489 |
| European Union Horizon 2020 Marie Skłodowska-Curie Fellowship | |
| Science Foundation Ireland | 13/RC/2094-P2 |
| Science Foundation Ireland |
Keywords
- Elliptic curves
- Field programmable gate array (FPGA)
- Hardware acceleration
- Montgomery curves
- Montgomery multiplication
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