A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|Publication status||Published - 1 Apr 2003|
- systolic arrays
Zhaohui, L., McCanny, J. V., Lightbody, G., & Walke, R. (2003). Generic SoC QR array processor for adaptive beamforming. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50(4), 169-175. https://doi.org/10.1109/TCSII.2003.810487