Generic SoC QR array processor for adaptive beamforming

L Zhaohui, J V McCanny, G Lightbody, R Walke

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.
Original languageEnglish
Pages (from-to)169-175
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Issue number4
Publication statusPublished (in print/issue) - 1 Apr 2003

Bibliographical note

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  • QR
  • RLS
  • VLSI
  • scheduling
  • mapping
  • systolic arrays


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