Generic SoC QR array processor for adaptive beamforming

L Zhaohui; J V McCanny; G Lightbody; R Walke

doi:10.1109/TCSII.2003.810487

Generic SoC QR array processor for adaptive beamforming

L Zhaohui, J V McCanny, G Lightbody, R Walke

Faculty Of Computing, Eng. & Built Env.

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.

Original language	English
Pages (from-to)	169-175
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	50
Issue number	4
DOIs	https://doi.org/10.1109/TCSII.2003.810487
Publication status	Published (in print/issue) - 1 Apr 2003

Bibliographical note

Reference text: [1] L. C. Godara, “Application of antenna arrays to mobile communications, Part II: Beam-forming and direction-of-arrival considerations,” in Proc. IEEE, vol. 85, Aug. 1997, pp. 1995–1245.
[2] S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice-Hall, 1995.
[3] J. M. Cioffi and T. Kailath, “Fast recursive-least-square, transversal filters for adaptive filtering,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 998–1005, Feb. 1984.
[4] S. F. Hsieh, K. J. R. Liu, and K.Yao, “A unified approach for QRD-based recursive least-squares estimation without square roots,” IEEE Trans. Signal Processing, vol. 41, pp. 1405–1409, Mar. 1993.
[5] W. M. Gentleman and H. T. Kung, “Matrix triangularization by systolic array,” in Proc. SPIE (Real-Time Signal Processing IV), 1973, pp. 329–369.
[6] J. G. McWhirter, “Recursive least squares minimization using systolic array,” in Proc. SPIE (Real-Time Signal Processing IV), vol. 431, 1983, pp. 105–112.
[7] T. J. Shepherd and J. G. McWhirter, “Systolic adaptive beamforming,” in Array Signal Processing, S. Haykin, J. Litva, and T. J. Shepherd, Eds. New York: Springer-Verlag, 1993, ch. 5, pp. 153–243.
[8] G. Lightbody, R. Walke, R. Woods, and J. McCanny, “Linear QR architecture for a single chip adaptive beamformer,” J. VLSI Signal Processing Syst. Signal, Image, Video Technol., vol. 24, pp. 67–81, 2000.
[9] J. G. McWhirter, R. L. Walke, and J. Kadlec, “Normalized givens rotations for recursive least squares processing,” VLSI Signal Processing, vol. VIII, pp. 323–332, 1995.
[10] R. L. Walke, “High sample rate givens rotations for recursive least squares,” Ph.D. dissertation, Univ. of Warwick, Coventry, U.K., 1997.
[11] R. Dohler, “Squared given’s rotation,” IMA J. Numer. Anal., vol. II, pp. 1–5, 1991.
[12] J. Gotze and U. Schwiegelshohn, “A square root free Givens rotation for solving least squares problems on systolic arrays,” SIAM J. Sci. Stat. Comput., vol. 4, pp. 800–807, 1991.
[13] J. McCanny, D. Ridge, Y. Hu, and J. Hunter, “Hierarchical VHDL libraries for DSP ASIC design,” in Proc. IEEE Int. Conf. Acoust., Speech and Signal Processing, Munich, Germany, pp. 675–678.
[14] C. M. Rader, “VLSI systolic arrays for adaptive nulling,” IEEE Signal Processing Mag., vol. 13, no. 4, pp. 29–49, 1996.
[15] (1999, Aug.) DSiPWare: Floating point library data book. [Online].
Available: http://www.amphion.com.

Keywords

QR
RLS
VLSI
scheduling
mapping
systolic arrays

Access to Document

10.1109/TCSII.2003.810487

Cite this

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title = "Generic SoC QR array processor for adaptive beamforming",

abstract = "A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.",

keywords = "QR, RLS, VLSI, scheduling, mapping, systolic arrays",

author = "L Zhaohui and McCanny, {J V} and G Lightbody and R Walke",

note = "Reference text: [1] L. C. Godara, “Application of antenna arrays to mobile communications, Part II: Beam-forming and direction-of-arrival considerations,” in Proc. IEEE, vol. 85, Aug. 1997, pp. 1995–1245. [2] S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice-Hall, 1995. [3] J. M. Cioffi and T. Kailath, “Fast recursive-least-square, transversal filters for adaptive filtering,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 998–1005, Feb. 1984. [4] S. F. Hsieh, K. J. R. Liu, and K.Yao, “A unified approach for QRD-based recursive least-squares estimation without square roots,” IEEE Trans. Signal Processing, vol. 41, pp. 1405–1409, Mar. 1993. [5] W. M. Gentleman and H. T. Kung, “Matrix triangularization by systolic array,” in Proc. SPIE (Real-Time Signal Processing IV), 1973, pp. 329–369. [6] J. G. McWhirter, “Recursive least squares minimization using systolic array,” in Proc. SPIE (Real-Time Signal Processing IV), vol. 431, 1983, pp. 105–112. [7] T. J. Shepherd and J. G. McWhirter, “Systolic adaptive beamforming,” in Array Signal Processing, S. Haykin, J. Litva, and T. J. Shepherd, Eds. New York: Springer-Verlag, 1993, ch. 5, pp. 153–243. [8] G. Lightbody, R. Walke, R. Woods, and J. McCanny, “Linear QR architecture for a single chip adaptive beamformer,” J. VLSI Signal Processing Syst. Signal, Image, Video Technol., vol. 24, pp. 67–81, 2000. [9] J. G. McWhirter, R. L. Walke, and J. Kadlec, “Normalized givens rotations for recursive least squares processing,” VLSI Signal Processing, vol. VIII, pp. 323–332, 1995. [10] R. L. Walke, “High sample rate givens rotations for recursive least squares,” Ph.D. dissertation, Univ. of Warwick, Coventry, U.K., 1997. [11] R. Dohler, “Squared given{\textquoteright}s rotation,” IMA J. Numer. Anal., vol. II, pp. 1–5, 1991. [12] J. Gotze and U. Schwiegelshohn, “A square root free Givens rotation for solving least squares problems on systolic arrays,” SIAM J. Sci. Stat. Comput., vol. 4, pp. 800–807, 1991. [13] J. McCanny, D. Ridge, Y. Hu, and J. Hunter, “Hierarchical VHDL libraries for DSP ASIC design,” in Proc. IEEE Int. Conf. Acoust., Speech and Signal Processing, Munich, Germany, pp. 675–678. [14] C. M. Rader, “VLSI systolic arrays for adaptive nulling,” IEEE Signal Processing Mag., vol. 13, no. 4, pp. 29–49, 1996. [15] (1999, Aug.) DSiPWare: Floating point library data book. [Online]. Available: http://www.amphion.com.",

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AB - A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.

KW - QR

KW - RLS

KW - VLSI

KW - scheduling

KW - mapping

KW - systolic arrays

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DO - 10.1109/TCSII.2003.810487

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JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IS - 4

ER -

Generic SoC QR array processor for adaptive beamforming

Abstract

Bibliographical note

Keywords

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