FPGA-Based Spiking Neural Network AutoEncoders for Real-Time Anomaly Detection in LHC Physics

Aqib Javed; Barry Dillon; Jim Harkin

doi:10.1109/ISCAS66217.2026.11561973

FPGA-Based Spiking Neural Network AutoEncoders for Real-Time Anomaly Detection in LHC Physics

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Abstract

Real-time anomaly detection at the Large Hadron Collider (LHC) requires ultra-low-latency inference under strict computational constraints. This paper presents the FPGA implementation of Spiking Neural Network AutoEncoders (SNN-AEs) for anomaly detection at the trigger level. Multiple SNN-AE architectures are synthesized on Xilinx UltraScale+ FPGAs and their resource utilization is characterized. Event-based spike processing reduces DSP usage by 67% and LUT usage by 53% compared to conventional Deep NN implementations while maintaining Area Under Curve (AUC) = 0.899 for charged Higgs-like scalar (h+) detection. The smallest SNN-AE architecture consumes only 1.99% LUTs and 1.94% DSPs, enabling viable integration into existing L1 trigger systems. Using the Compact Muon Solenoid (CMS) ADC2021 dataset, hardware resource comparisons are provided with FPGA-deployed DNN AutoEncoders across multiple signal models and architectural configurations.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	4172-4176
Number of pages	5
ISBN (Electronic)	979-8-3315-7769-8
ISBN (Print)	979-8-3315-7770-4
DOIs	https://doi.org/10.1109/ISCAS66217.2026.11561973
Publication status	Published online - 18 Jun 2026
Event	2026 IEEE International Symposium on Circuits and Systems (ISCAS) - Shanghai, China Duration: 24 May 2026 → 28 May 2026

Publication series

Name
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Country/Territory	China
City	Shanghai
Period	24/05/26 → 28/05/26

Bibliographical note

Publisher Copyright:
© 2026 IEEE.

Funding

Computing resources provided by the Northern Ireland High Performance Computing (NI-HPC) service funded by EPSRC (EP/T022175).

Funders	Funder number
Engineering and Physical Sciences Research Council	EP/T022175

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Keywords

LHC physics
FPGA
Neuromorphic Computing
Spiking Neural Networks (SNNs)
Anomaly Detection
machine-learning
spiking neural networks
anomaly detection
neuromorphic computing

Access to Document

10.1109/ISCAS66217.2026.11561973

Aqib_ISCAS_2026_FinalAuthor Accepted Manuscript, 816 KB

Cite this

@inproceedings{4384288934014493a8e2b6fee82874bb,

title = "FPGA-Based Spiking Neural Network AutoEncoders for Real-Time Anomaly Detection in LHC Physics",

abstract = "Real-time anomaly detection at the Large Hadron Collider (LHC) requires ultra-low-latency inference under strict computational constraints. This paper presents the FPGA implementation of Spiking Neural Network AutoEncoders (SNN-AEs) for anomaly detection at the trigger level. Multiple SNN-AE architectures are synthesized on Xilinx UltraScale+ FPGAs and their resource utilization is characterized. Event-based spike processing reduces DSP usage by 67\% and LUT usage by 53\% compared to conventional Deep NN implementations while maintaining Area Under Curve (AUC) = 0.899 for charged Higgs-like scalar (h+) detection. The smallest SNN-AE architecture consumes only 1.99\% LUTs and 1.94\% DSPs, enabling viable integration into existing L1 trigger systems. Using the Compact Muon Solenoid (CMS) ADC2021 dataset, hardware resource comparisons are provided with FPGA-deployed DNN AutoEncoders across multiple signal models and architectural configurations.",

keywords = "LHC physics, FPGA, Neuromorphic Computing, Spiking Neural Networks (SNNs), Anomaly Detection, machine-learning, spiking neural networks, anomaly detection, neuromorphic computing",

author = "Aqib Javed and Barry Dillon and Jim Harkin",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 24-05-2026 Through 28-05-2026",

year = "2026",

month = jun,

day = "18",

doi = "10.1109/ISCAS66217.2026.11561973",

language = "English",

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T1 - FPGA-Based Spiking Neural Network AutoEncoders for Real-Time Anomaly Detection in LHC Physics

AU - Javed, Aqib

AU - Dillon, Barry

AU - Harkin, Jim

PY - 2026/6/18

Y1 - 2026/6/18

N2 - Real-time anomaly detection at the Large Hadron Collider (LHC) requires ultra-low-latency inference under strict computational constraints. This paper presents the FPGA implementation of Spiking Neural Network AutoEncoders (SNN-AEs) for anomaly detection at the trigger level. Multiple SNN-AE architectures are synthesized on Xilinx UltraScale+ FPGAs and their resource utilization is characterized. Event-based spike processing reduces DSP usage by 67% and LUT usage by 53% compared to conventional Deep NN implementations while maintaining Area Under Curve (AUC) = 0.899 for charged Higgs-like scalar (h+) detection. The smallest SNN-AE architecture consumes only 1.99% LUTs and 1.94% DSPs, enabling viable integration into existing L1 trigger systems. Using the Compact Muon Solenoid (CMS) ADC2021 dataset, hardware resource comparisons are provided with FPGA-deployed DNN AutoEncoders across multiple signal models and architectural configurations.

AB - Real-time anomaly detection at the Large Hadron Collider (LHC) requires ultra-low-latency inference under strict computational constraints. This paper presents the FPGA implementation of Spiking Neural Network AutoEncoders (SNN-AEs) for anomaly detection at the trigger level. Multiple SNN-AE architectures are synthesized on Xilinx UltraScale+ FPGAs and their resource utilization is characterized. Event-based spike processing reduces DSP usage by 67% and LUT usage by 53% compared to conventional Deep NN implementations while maintaining Area Under Curve (AUC) = 0.899 for charged Higgs-like scalar (h+) detection. The smallest SNN-AE architecture consumes only 1.99% LUTs and 1.94% DSPs, enabling viable integration into existing L1 trigger systems. Using the Compact Muon Solenoid (CMS) ADC2021 dataset, hardware resource comparisons are provided with FPGA-deployed DNN AutoEncoders across multiple signal models and architectural configurations.

KW - LHC physics

KW - FPGA

KW - Neuromorphic Computing

KW - Spiking Neural Networks (SNNs)

KW - Anomaly Detection

KW - machine-learning

KW - spiking neural networks

KW - anomaly detection

KW - neuromorphic computing

UR - https://pure.ulster.ac.uk/en/publications/43842889-3401-4493-a8e2-b6fee82874bb

UR - https://www.scopus.com/pages/publications/105043472949

U2 - 10.1109/ISCAS66217.2026.11561973

DO - 10.1109/ISCAS66217.2026.11561973

M3 - Conference contribution

SN - 979-8-3315-7770-4

SP - 4172

EP - 4176

BT - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 2026 IEEE International Symposium on Circuits and Systems (ISCAS)

Y2 - 24 May 2026 through 28 May 2026

ER -

FPGA-Based Spiking Neural Network AutoEncoders for Real-Time Anomaly Detection in LHC Physics

Abstract

Publication series

Conference

Bibliographical note

Funding

UN SDGs

Keywords

Access to Document

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Cite this