Fixed Latency On-Chip Interconnect for Hardware Spiking Neural Network Architectures

Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes.Distortion in spike timings can impact the accuracy of SNN operation by modifying the precisefiring time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructureoffers scalable connectivity for spike communication in hardware SNN architectures. However,shared resources in NoC architectures can result in unwanted variation in spike packet transferlatency. This packet latency jitter distorts the timing information conveyed on the synapticconnections in the SNN, resulting in unreliable application behaviour.This paper presents a SystemC simulation based analysis of the synaptic information distortionin NoC based hardware SNNs. The paper proposes a fixed spike transfer latency ringtopology interconnect for spike communication between neural tiles, using a novel timestampedspike broadcast flow control scheme. The proposed architectural technique is evaluated usingspike rates employed in previously reported mesh topology NoC based hardware SNN applications,which exhibited spike latency jitter over NoC paths. Results indicate that the proposedinterconnect offers fixed spike transfer latency and eliminates the associated information distortion.The paper presents the micro-architecture of the proposed ring router. The FPGA validatedring interconnect architecture has been synthesised using 65nm low-power CMOS technology.Silicon area comparisons for various ring sizes are presented. Scalability of the proposed architecture has been addressed by employing a hierarchical NoC architecture.