Field programmable gate array based parallel matrix multiplier for 3D affine transformations

F. Bensaali, A Amira

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic.
    LanguageEnglish
    Pages739-746
    JournalIEE Proceedings - Vision Image and Signal Processing
    Volume153
    Issue number6
    DOIs
    Publication statusPublished - Dec 2006

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    Particle accelerators
    Field programmable gate arrays (FPGA)
    Fixed point arithmetic
    Digital arithmetic
    Computer aided design
    Visualization
    Processing

    Cite this

    Bensaali, F. ; Amira, A. / Field programmable gate array based parallel matrix multiplier for 3D affine transformations. 2006 ; Vol. 153, No. 6. pp. 739-746.
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    Field programmable gate array based parallel matrix multiplier for 3D affine transformations. / Bensaali, F.; Amira, A.

    Vol. 153, No. 6, 12.2006, p. 739-746.

    Research output: Contribution to journalArticle

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