The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.
|Title of host publication||2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)|
|Publication status||Published - 6 Jan 2018|
|Event||2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Pune, India|
Duration: 6 Jan 2018 → 10 Jan 2018
|Conference||2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)|
|Period||6/01/18 → 10/01/18|