Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Haji Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, LJ McDaid, David M. Halliday

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.
LanguageEnglish
Title of host publication 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
DOIs
Publication statusPublished - 6 Jan 2018
Event2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Pune, India
Duration: 6 Jan 201810 Jan 2018

Conference

Conference2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
CountryIndia
CityPune
Period6/01/1810/01/18

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Plasticity
Field programmable gate arrays (FPGA)
Neural networks
Neurons
Fault tolerance
Network performance
Robotics
Astrocytes

Cite this

Johnson, A. P., Liu, J., Millard, A. G., Haji Karim, S., Tyrrell, A. M., Harkin, J., ... Halliday, D. M. (2018). Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) https://doi.org/10.1109/VLSID.2018.36
Johnson, Anju P. ; Liu, Junxiu ; Millard, Alan G. ; Haji Karim, Shvan ; Tyrrell, Andy M. ; Harkin, Jim ; Timmis, Jon ; McDaid, LJ ; Halliday, David M. / Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). 2018.
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Johnson, AP, Liu, J, Millard, AG, Haji Karim, S, Tyrrell, AM, Harkin, J, Timmis, J, McDaid, LJ & Halliday, DM 2018, Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 6/01/18. https://doi.org/10.1109/VLSID.2018.36

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. / Johnson, Anju P.; Liu, Junxiu; Millard, Alan G.; Haji Karim, Shvan; Tyrrell, Andy M.; Harkin, Jim; Timmis, Jon; McDaid, LJ; Halliday, David M.

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). 2018.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

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AU - Liu, Junxiu

AU - Millard, Alan G.

AU - Haji Karim, Shvan

AU - Tyrrell, Andy M.

AU - Harkin, Jim

AU - Timmis, Jon

AU - McDaid, LJ

AU - Halliday, David M.

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N2 - The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

AB - The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

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DO - 10.1109/VLSID.2018.36

M3 - Conference contribution

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Johnson AP, Liu J, Millard AG, Haji Karim S, Tyrrell AM, Harkin J et al. Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). 2018 https://doi.org/10.1109/VLSID.2018.36