Fan-In analysis of a leaky integrator circuit using charge transfer synapses

Thomas Dowrick; LJ McDaid; Stephen Hall

doi:10.1016/j.neucom.2018.06.065

Fan-In analysis of a leaky integrator circuit using charge transfer synapses

Thomas Dowrick, LJ McDaid, Stephen Hall

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

28 Downloads (Pure)

Abstract

It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.

Original language	English
Pages (from-to)	78-85
Number of pages	8
Journal	Neurocomputing
Volume	314
Early online date	4 Jul 2018
DOIs	https://doi.org/10.1016/j.neucom.2018.06.065
Publication status	Published (in print/issue) - 7 Nov 2018

Keywords

Neuromorphic circuits
Fan-in
Spiking neural network
Leaky Integrator
Charge Transfer Synapse
CMOS

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1016/j.neucom.2018.06.065Licence: Unspecified

Fan-in-paper-revisionAuthor Accepted Manuscript, 541 KB

Cite this

@article{09552d6662244773bb6d2829adbee84a,

title = "Fan-In analysis of a leaky integrator circuit using charge transfer synapses",

abstract = "It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs. ",

keywords = "Neuromorphic circuits, Fan-in, Spiking neural network, Leaky Integrator , Charge Transfer Synapse, CMOS",

author = "Thomas Dowrick and LJ McDaid and Stephen Hall",

year = "2018",

month = nov,

day = "7",

doi = "10.1016/j.neucom.2018.06.065",

language = "English",

volume = "314",

pages = "78--85",

journal = "Neurocomputing",

publisher = "Elsevier",

}

TY - JOUR

T1 - Fan-In analysis of a leaky integrator circuit using charge transfer synapses

AU - Dowrick, Thomas

AU - McDaid, LJ

AU - Hall, Stephen

PY - 2018/11/7

Y1 - 2018/11/7

N2 - It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.

AB - It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.

KW - Neuromorphic circuits

KW - Fan-in

KW - Spiking neural network

KW - Leaky Integrator

KW - Charge Transfer Synapse

KW - CMOS

UR - https://pure.ulster.ac.uk/en/publications/fan-in-analysis-of-a-leaky-integrator-circuit-using-charge-transf

U2 - 10.1016/j.neucom.2018.06.065

DO - 10.1016/j.neucom.2018.06.065

M3 - Article

VL - 314

SP - 78

EP - 85

JO - Neurocomputing

JF - Neurocomputing

ER -

Fan-In analysis of a leaky integrator circuit using charge transfer synapses

Abstract

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this