Fan-In Analysis of a Leaky Integrator Circuit Using Charge Transfer Synapses

Thomas Dowrick, LJ McDaid, Steve Hall

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It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.
Original languageEnglish
Pages (from-to)78-85
Early online date4 Jul 2018
Publication statusPublished - 7 Nov 2018


  • Neuromorphic circuits
  • Fan-in
  • Spiking neural network
  • Leaky Integrator
  • Charge Transfer Synapse
  • CMOS

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