EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

Sandeep Pande, Fearghal Morgan, Seamus McCawley, Brian McGinely, Sanider Carrillo, Jim Harkin, Liam McDaid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.
Original languageEnglish
Title of host publicationUnknown Host Publication
Number of pages7
Publication statusPublished - 28 Sep 2010
EventInternational Symposium on System-on-Chip (SoC) - Finland
Duration: 28 Sep 2010 → …

Conference

ConferenceInternational Symposium on System-on-Chip (SoC)
Period28/09/10 → …

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Cite this

Pande, S., Morgan, F., McCawley, S., McGinely, B., Carrillo, S., Harkin, J., & McDaid, L. (2010). EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures. In Unknown Host Publication