EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

Sandeep Pande; Fearghal Morgan; Seamus McCawley; Brian McGinely; Sanider Carrillo; Jim Harkin; Liam McDaid

EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

Sandeep Pande, Fearghal Morgan, Seamus McCawley, Brian McGinely, Sanider Carrillo, Jim Harkin, Liam McDaid

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.

Original language	English
Title of host publication	Unknown Host Publication
Publisher	IEEE
Number of pages	7
Publication status	Published (in print/issue) - 28 Sept 2010
Event	International Symposium on System-on-Chip (SoC) - Finland Duration: 28 Sept 2010 → …

Conference

Conference	International Symposium on System-on-Chip (SoC)
Period	28/09/10 → …

Cite this

@inproceedings{a04cd23242d4436e9642d1a7df40ece6,

title = "EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures",

abstract = "This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.",

author = "Sandeep Pande and Fearghal Morgan and Seamus McCawley and Brian McGinely and Sanider Carrillo and Jim Harkin and Liam McDaid",

year = "2010",

month = sep,

day = "28",

language = "English",

booktitle = "Unknown Host Publication",

publisher = "IEEE",

address = "United States",

note = "International Symposium on System-on-Chip (SoC) ; Conference date: 28-09-2010",

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TY - GEN

T1 - EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

AU - Pande, Sandeep

AU - Morgan, Fearghal

AU - McCawley, Seamus

AU - McGinely, Brian

AU - Carrillo, Sanider

AU - Harkin, Jim

AU - McDaid, Liam

PY - 2010/9/28

Y1 - 2010/9/28

N2 - This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.

AB - This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.

M3 - Conference contribution

BT - Unknown Host Publication

PB - IEEE

T2 - International Symposium on System-on-Chip (SoC)

Y2 - 28 September 2010

ER -

EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

Abstract

Conference

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