Efficient Wafer Defect Patterns Recognition Using Deep Convolutional Neural Network

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Defect recognition in semiconductor wafers is crucial in manufacturing process to identify the root cause. This paper presents an efficient wafer defects pattern recognition methodology based on deep convolutional neural networks (DCNN) to automate the classification. In DCNN design, we revamped LeNet-5 deep learning model. The proposed DCNN comprises seven layers including three convolutional and two pooling layers. We implemented an adaptive moment (Adam) optimizer to fine-tune model parameters in DCNN. We tested the proposed model on publicly available semiconductor wafers datasets to verify the effectiveness of the model. The experimental study suggests that the proposed model is highly efficient in classifying wafer defects with an accuracy of 99.22% in testing.
Original languageEnglish
Title of host publication2023 IEEE Conference on Artificial Intelligence (CAI)
Number of pages2
ISBN (Electronic)979-8-3503-3984-0
ISBN (Print)979-8-3503-3985-7
Publication statusPublished online - 2 Aug 2023
Event2023 IEEE Conference on Artificial Intelligence - Hyatt Regency Santa Clara 5101 Great America Parkway, California, United States
Duration: 5 Jun 20236 Jun 2023

Publication series

NameProceedings - 2023 IEEE Conference on Artificial Intelligence, CAI 2023


Conference2023 IEEE Conference on Artificial Intelligence
Country/TerritoryUnited States
Internet address

Bibliographical note

Publisher Copyright:
© 2023 IEEE.


  • Semiconductor wafer
  • smart manufacturing
  • pattern recognition
  • deep learning


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