Efficient neuron architecture for FPGA-based spiking neural networks

Lei Wan; Yuling Luo; Shuxiang Song; Jim Harkin; Junxiu Liu

doi:10.1109/ISSC.2016.7528472

Efficient neuron architecture for FPGA-based spiking neural networks

Lei Wan, Yuling Luo, Shuxiang Song, Jim Harkin, Junxiu Liu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Citations (Scopus)

142 Downloads (Pure)

Abstract

Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources. The neuron computing core is developed as the key component for the neuron model computation, which is shared by multiple synapses within one neuron cell; and also the computing component of one neuron is shared by several neurons within one layer of the SNN system. A test bench experiment is designed for a Xilinx FPGA device and the results demonstrate that the proposed ENA occupies relatively low hardware resources and has the capability to scale for large SNN implementations.

Original language	English
Title of host publication	Unknown Host Publication
Publisher	Institution of Engineering and Technology
Pages	1-6
Number of pages	6
DOIs	https://doi.org/10.1109/ISSC.2016.7528472
Publication status	Accepted/In press - 5 May 2016
Event	27th Irish Signals and Systems Conference (ISSC) - Duration: 5 May 2016 → …

Conference

Conference	27th Irish Signals and Systems Conference (ISSC)
Period	5/05/16 → …

Keywords

field programmable gate arrays
neural nets
ENA
FPGA-based spiking neural networks
Xilinx FPGA device
computing component sharing mechanism
digital SNN
digital spiking neural networks
efficient neuron architecture
hardware SNNs
neuron computing core
neuron model computation
silicon area reduction
Computational modeling
Computer architecture
Hardware
Integrated circuit modeling
Neurons
Random access memory
Topology
FPGA implementation
efficient design
sharing mechanism
spiking neural networks

Access to Document

10.1109/ISSC.2016.7528472

IET ISSC 2016Author Accepted Manuscript, 429 KB
SNN tdm impl v12 5Author Accepted Manuscript, 566 KB

Cite this

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title = "Efficient neuron architecture for FPGA-based spiking neural networks",

abstract = "Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources. The neuron computing core is developed as the key component for the neuron model computation, which is shared by multiple synapses within one neuron cell; and also the computing component of one neuron is shared by several neurons within one layer of the SNN system. A test bench experiment is designed for a Xilinx FPGA device and the results demonstrate that the proposed ENA occupies relatively low hardware resources and has the capability to scale for large SNN implementations.",

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author = "Lei Wan and Yuling Luo and Shuxiang Song and Jim Harkin and Junxiu Liu",

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AU - Luo, Yuling

AU - Song, Shuxiang

AU - Harkin, Jim

AU - Liu, Junxiu

PY - 2016/5/5

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N2 - Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources. The neuron computing core is developed as the key component for the neuron model computation, which is shared by multiple synapses within one neuron cell; and also the computing component of one neuron is shared by several neurons within one layer of the SNN system. A test bench experiment is designed for a Xilinx FPGA device and the results demonstrate that the proposed ENA occupies relatively low hardware resources and has the capability to scale for large SNN implementations.

AB - Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources. The neuron computing core is developed as the key component for the neuron model computation, which is shared by multiple synapses within one neuron cell; and also the computing component of one neuron is shared by several neurons within one layer of the SNN system. A test bench experiment is designed for a Xilinx FPGA device and the results demonstrate that the proposed ENA occupies relatively low hardware resources and has the capability to scale for large SNN implementations.

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KW - neural nets

KW - ENA

KW - FPGA-based spiking neural networks

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KW - computing component sharing mechanism

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KW - digital spiking neural networks

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KW - neuron computing core

KW - neuron model computation

KW - silicon area reduction

KW - Computational modeling

KW - Computer architecture

KW - Hardware

KW - Integrated circuit modeling

KW - Neurons

KW - Random access memory

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KW - efficient design

KW - sharing mechanism

KW - spiking neural networks

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T2 - 27th Irish Signals and Systems Conference (ISSC)

Y2 - 5 May 2016

ER -

Efficient neuron architecture for FPGA-based spiking neural networks

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Keywords

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