Device-circuit co-design of an energy-efficient VGSOT-MTJ based logic-in-memory multiplexer and APUF enabled hardware security

Multiplexer (MUX) designs are vital for boosting system performance by achieving high speeds, reducing design complexity, and lowering power consumption and costs. Spintronic devices, particularly magnetic tunnel junctions (MTJs), address CMOS limitations at smaller footprints. Among these, the voltage–gated spin–orbit torque (VGSOT)–based MTJ, using voltage–controlled magnetic anisotropy (VCMA) and in–plane exchange bias (HEX), stands out for creating low–power, high–speed circuits. This study introduces a hybrid VGSOT–MTJ/CMOS logic–in–memory (LIM) 2:1 MUX, leveraging VGSOT–MTJ and LIM benefits for enhanced performance. Simulations with Cadence Virtuoso at the 45 nm technology node validate the design, incorporating an electrical VGSOT–MTJ model. Results show an 87.02%, 44.17%, 36.03%, and 61.72% reduction in power consumption compared to CMOS, STT–MTJ and state–of–the–art design, respectively, along with 73.86%, 53.58%, 70.28%, and 42.59% improvements in delay. Energy efficiency also increases by 96.6%, 74.10%, 78.18%, and 77.96% over CMOS, STT–MTJ, and existing designs. Additionally, VGSOT–MTJ’s potential in hardware security is explored through single–cell entropy assessments, revealing high entropy at low voltages. Furthermore, the proposed VGSOT–MTJ/CMOS 2:1 MUX was utilized to design an arbiter physically unclonable function (APUF), and its performance was evaluated under varying environmental conditions. Performance metrics such as uniqueness, uniformity, bit–aliasing and reliability were achieved close to ideal. These findings highlight the suitability of VGSOT–MTJ for energy–efficient and hardware–secure primitive design in hardware security applications.