Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures

A Amira, A Bouridane, P Milligan, A Belatreche

    Research output: Contribution to journalArticle

    11 Citations (Scopus)

    Abstract

    Discrete orthogonal transforms (DOTs) are important in many applications, including image and signal processing. Novel 1D and 2D bit-level systolic architectures are presented for the efficient implementation of DOTs for image and signal processing. The authors describe the design methodology of the techniques based on the Baugh-Wooley algorithm, and the associated design including a case study of an FPGA implementation. They also discuss the efficiency of implementations which have O(N-2) and O(2nN) as the area and time complexities for 2D structures, respectively, and O(N) and O(2nN) as the area and time complexities for 1D structures, respectively (where N is the transform length and n is the word length). Furthermore, it is shown that the architectures are parameterisable and that the area required by the designs can be predicted for different values of N and n. A comparison with existing and similar structures has shown that the proposed architectures perform better.
    Original languageEnglish
    Pages (from-to)17-24
    JournalIEE Proceedings - Computers and Digital Techniques
    Volume149
    Issue number1
    DOIs
    Publication statusPublished - Jan 2002

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