Design of a parameterizable silicon intellectual property core for QR-based RLS filtering

G. Lightbody, R. Woods, R. Walke

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.
Original languageEnglish
Pages (from-to)659-678
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number4
DOIs
Publication statusPublished - 1 Aug 2003

Keywords

  • Arithmetic
  • Circuits
  • Filtering algorithms
  • Hardware design languages
  • Intellectual property
  • Least mean square algorithms
  • Least squares methods
  • Resonance light scattering
  • Silicon
  • Timing

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