### Abstract

Language | English |
---|---|

Pages | 659-678 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 11 |

Issue number | 4 |

DOIs | |

Publication status | Published - 1 Aug 2003 |

### Fingerprint

### Keywords

- Arithmetic
- Circuits
- Filtering algorithms
- Hardware design languages
- Intellectual property
- Least mean square algorithms
- Least squares methods
- Resonance light scattering
- Silicon
- Timing

### Cite this

*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*,

*11*(4), 659-678. https://doi.org/10.1109/TVLSI.2003.816142

}

*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 11, no. 4, pp. 659-678. https://doi.org/10.1109/TVLSI.2003.816142

**Design of a parameterizable silicon intellectual property core for QR-based RLS filtering.** / Lightbody, G.; Woods, R.; Walke, R.

Research output: Contribution to journal › Article

TY - JOUR

T1 - Design of a parameterizable silicon intellectual property core for QR-based RLS filtering

AU - Lightbody, G.

AU - Woods, R.

AU - Walke, R.

N1 - Reference text: 1.J. V. McCanny, D. Ridge, Y. Yu, and J. Hunter, "Hierarchical VHDL libraries for DSP ASIC design ", Proc Int. Acoustics, Speech, Signal Processing Conf. , pp.675 - 678 , 1997. 2. J. G. McWhirter, "Recursive least squares minimization using systolic array", Proc. SPIE, pp.105 - 112 , 1983. 3. C. M. Rader, "VLSI systolic arrays for adaptive nulling", IEEE Signal Processing Mag., vol. 13, pp.29 - 49 , 1996. 4. G. Lightbody, R. Woods, R. Walke, J. McCanny, Y. Hu, and D. Trainor, "Rapid design of a single chip adaptive beamformer ", Proc. IEEE Signal Processing Systems, Design, Implementation Workshop, pp.285 - 294 , 1998. 5. R. L. Walke, High sample rate givens rotations for recursive least squares, , 1997. :Dept. Comput. Sci., Univ. Warwick 6. T. J. Shephard and J. G. McWhirter, S. Haykin, J. Litva, and T. J. Shephard, "Systolic adaptive beamforming ", Array Processing, pp. 153 - 243 , 1993. :Springer-Verlag 7. W. Givens, "Computation of plane unitary rotations transforming a general matrix to triangular form", J. Soc. Ind. Applicat. Math., vol. 6, pp.26 - 50 , 1958. 8. J. Cioffi, "The fast householder filters RLS adaptive algorithm RLS adaptive filter", Proc. Int. Acoustics, Speech, Signal Processing Conf., pp. 1619 - 1621 , 1990. 9. C. M. Rader and A. O. Steinhardt, "Hyperbolic householder transformations, definition and applications", Proc. Int. Acoustics, Speech, Signal Processing Conf., pp. 2511 - 2514 , 1986. 10. K. J. R. Liu, S. Hsieh, and K. Yao, "Recursive LS filtering using block householder transformations", Proc. Int. Acoustics, Speech, Signal Processing Conf., pp.1631 - 1634 , 1990. 11. K. J. R. Liu, S. Hsieh, and K. Yao, "Systolic block householder transformations for RLS algorithm with two-level pipelined implementation", IEEE Trans. Signal Processing, vol. 40, pp.946 - 958 , 1992. 12. R. D\öhler, "Squared Given's rotations", IMA J. Numer. Analysis, vol. II, pp.1 - 5 , 1991. 13. J. M. Cioffi and T. Kailath, "Fast recursive-least-square, transversal filters for adaptive filtering", IEEE Trans. Acoustics, Speech, Signal Processing, vol. ASSP-32, pp.998 - 1005 , 1984. 14. S. F. Hsieh, K. J. R. Liu, and K. Yao, "A unified approach for QRD-based recursive least-squares estimation without square roots", IEEE Trans. Signal Processing, vol. 41, pp.1405 - 1409 , 1993. 15. C. M. Rader, "MUSE: A systolic array for adaptive nulling with 64 degrees of freedom using the givens transformations and wafer scale integration", Proc. Int. Applications Specific Array Processors Conf., pp.227 - 291 , 1992. 16. C. M. Rader, "VLSI systolic arrays for adaptive nulling", IEEE Signal Processing Mag., vol. 13, pp.29 - 49 , 1996. 17. R. Hamill, VLSI algorithms and architectures for DSP arithmetic computations, , 1995. :Dept. Elect. Electron. Eng., Queen's Univ. Belfast 18. G. Lightbody, High performance VLSI architectures for recursive least squares filtering , , 2000. :Dept. Elect. Electron. Eng., Queen's Univ. Belfast 19. D. Trainor, R. F. Woods, and J. V. McCanny, "Architectural synthesis of digital signal processing algorithms using \“IRIS\”", J. VLSI Signal Processing , vol. 16, no. 1, pp.41 - 56 , 1997. 20. S. Y. Kung, "On supercomputing with systolic/wavefront array processors", Proc. IEEE, vol. 72, pp.867 - 884 , 1984. 21. C. E. Leiserson, et al., "Optimizing synchronous circuitry by retiming", Proc. 3rd Caltech VLSI Conf., pp.87 - 116 , 1983.

PY - 2003/8/1

Y1 - 2003/8/1

N2 - The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.

AB - The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.

KW - Arithmetic

KW - Circuits

KW - Filtering algorithms

KW - Hardware design languages

KW - Intellectual property

KW - Least mean square algorithms

KW - Least squares methods

KW - Resonance light scattering

KW - Silicon

KW - Timing

U2 - 10.1109/TVLSI.2003.816142

DO - 10.1109/TVLSI.2003.816142

M3 - Article

VL - 11

SP - 659

EP - 678

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

ER -