TY - JOUR

T1 - Design of a parameterizable silicon intellectual property core for QR-based RLS filtering

AU - Lightbody, G.

AU - Woods, R.

AU - Walke, R.

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PY - 2003/8/1

Y1 - 2003/8/1

N2 - The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.

AB - The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.

KW - Arithmetic

KW - Circuits

KW - Filtering algorithms

KW - Hardware design languages

KW - Intellectual property

KW - Least mean square algorithms

KW - Least squares methods

KW - Resonance light scattering

KW - Silicon

KW - Timing

U2 - 10.1109/TVLSI.2003.816142

DO - 10.1109/TVLSI.2003.816142

M3 - Article

VL - 11

SP - 659

EP - 678

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

ER -