Bio-Inspired Online Fault Detection in NoC Interconnect

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Technology scaling over the years has enabled the integration of multi-ple processing cores on a single chip with Network-on-chip (NoC) becoming aninterconnect standard for facilitating large scale connectivity between cores. How-ever, these NoC components, like any other circuit components, are also becomingmore susceptible to faults with further scaling. The ability to adapt and perform re-liably in the presence of these faults is an emerging design challenge for NoC-basedmultiprocessor systems. A crucial requirement for such designs is to effectively de-tect the faults during runtime, in particular with the ability to differentiate betweentemporary and permanent faults. Developing interconnect architectures with online,low-cost fault detection capabilities remains largely unaddressed and is a major de-sign challenge for current and future scalable NoC-based multiprocessor systems.This chapter introduces SMART, a novel "real-time" strategy for detecting faults inNoC interconnect by using biological synapses and neurons to detect temporal andspatial faults. Analysis of fault scenarios and results from real-time experimentson an FPGA implementation of SMART using the example EMBRACE NoC areprovided.
Original languageEnglish
Title of host publicationEnergy Efficient Fault Tolerant Systems
EditorsJ Mathew, RA Shafik, D Pradhan
PublisherSpringer
Pages241-268
ISBN (Print)978-1-4614-4192-2
DOIs
Publication statusPublished - 12 Jul 2013

Keywords

  • Networks-on-chip
  • Fault detection
  • Neural networks
  • Hardware
  • FPGA

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