Bio-inspired fault detection circuits based on synapse and spiking neuron models

Junxiu Liu, Yongchuang Huang, Yuling Luo, Jim Harkin, Liam McDaid

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems.

LanguageEnglish
Pages473-482
Number of pages10
JournalNeurocomputing
Volume331
DOIs
Publication statusPublished - 28 Feb 2019

Fingerprint

Fault detection
Synapses
Neurons
Memristors
Networks (circuits)
Equipment and Supplies
Hardware
Fault tolerance
Transistors
Fires
Electric power utilization
Electric potential

Keywords

  • Fault detection
  • Memristive synapses
  • Memristor
  • Spiking neuron model

Cite this

@article{6d2550f8b23d466181308cf92e5f9747,
title = "Bio-inspired fault detection circuits based on synapse and spiking neuron models",
abstract = "Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems.",
keywords = "Fault detection, Memristive synapses, Memristor, Spiking neuron model",
author = "Junxiu Liu and Yongchuang Huang and Yuling Luo and Jim Harkin and Liam McDaid",
note = "Title Neurocomputing Deposit Requirement - https://ref.sherpa.ac.uk/compliance/0925-2312/AB Deposit the full text of the Accepted Version of your article in an Institutional Repository or a Subject Repository within 3 months of acceptance, with restricted access.",
year = "2019",
month = "2",
day = "28",
doi = "10.1016/j.neucom.2018.11.078",
language = "English",
volume = "331",
pages = "473--482",

}

Bio-inspired fault detection circuits based on synapse and spiking neuron models. / Liu, Junxiu; Huang, Yongchuang; Luo, Yuling; Harkin, Jim; McDaid, Liam.

Vol. 331, 28.02.2019, p. 473-482.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Bio-inspired fault detection circuits based on synapse and spiking neuron models

AU - Liu, Junxiu

AU - Huang, Yongchuang

AU - Luo, Yuling

AU - Harkin, Jim

AU - McDaid, Liam

N1 - Title Neurocomputing Deposit Requirement - https://ref.sherpa.ac.uk/compliance/0925-2312/AB Deposit the full text of the Accepted Version of your article in an Institutional Repository or a Subject Repository within 3 months of acceptance, with restricted access.

PY - 2019/2/28

Y1 - 2019/2/28

N2 - Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems.

AB - Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems.

KW - Fault detection

KW - Memristive synapses

KW - Memristor

KW - Spiking neuron model

UR - http://www.scopus.com/inward/record.url?scp=85057965065&partnerID=8YFLogxK

U2 - 10.1016/j.neucom.2018.11.078

DO - 10.1016/j.neucom.2018.11.078

M3 - Article

VL - 331

SP - 473

EP - 482

ER -