Astrocyte to spiking neuron communication using Networks-on-Chip ring topology

Hardware faults are becoming more frequent due to geometric scaling, reducing the reliability and lifespan of devices. Current fault-tolerant approaches use redundancy or a central controller to detect and/or repair faults. However, these methods are also susceptible to faults. Astrocytes have been shown to facilitate biological self-repair in silent or near silent neurons in the brain by increasing the Probability of Release (PR) in healthy synapses. Astrocytes modulate synaptic activity, which leads to increased or decreased PR. To date, this has been proven with computational modelling and therefore the next step is to replicate this self-repair process in hardware to provide self-repairing systems. One of the key challenges for hardware neuro-glia networks is the facilitation of scalable communication between interacting neurons and astrocyte cells. This paper contributes a low-level Networks-on-Chip (NoC) ring topology for astrocyte to neuron/synapse communication which provides a scalable solution to this interconnect challenge. It builds upon our previous FPGA-based Hierarchical Networks-on-Chip (HNoC) and establishes preliminary communication building blocks to facilitate the development of distributed self-repair hardware systems. FPGA results demonstrate that the new ring topology provides a good trade-off between low area/interconnect wiring overhead and communication speed for the relatively slow-changing data between astrocyte and neurons.