Architectures for adaptive weight calculation on ASIC and FPGA

R.L. Walke, R.W.M. Smith, G Lightbody

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)
17 Downloads (Pure)

Abstract

We compare two parallel urray architectures for adaptive weight calculation based on QR-decomposition by Givens Rotations. We present FPGA implementations of borh orchitectures und compare them with un ASIC-bused solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost ure not critical.
Original languageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationOnline
PublisherIEEE
Pages1375-1380
Number of pages6
ISBN (Print)0-7803-5700-0
DOIs
Publication statusPublished - 6 Aug 2002
EventConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999. - Pacific Grove, CA, USA , USA
Duration: 6 Aug 2002 → …

Conference

ConferenceConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999.
Period6/08/02 → …

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Keywords

  • QR-RLS
  • VLSI
  • VHDL
  • CORDIC
  • systolic arrays

Cite this

Walke, R. L., Smith, R. W. M., & Lightbody, G. (2002). Architectures for adaptive weight calculation on ASIC and FPGA. In Unknown Host Publication (pp. 1375-1380). Online: IEEE. https://doi.org/10.1109/ACSSC.1999.831931