Architectures for adaptive weight calculation on ASIC and FPGA

R.L. Walke; R.W.M. Smith; G Lightbody

doi:10.1109/ACSSC.1999.831931

Architectures for adaptive weight calculation on ASIC and FPGA

R.L. Walke, R.W.M. Smith, G Lightbody

Faculty Of Computing, Eng. & Built Env.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

33 Citations (Scopus)

135 Downloads (Pure)

Abstract

We compare two parallel urray architectures for adaptive weight calculation based on QR-decomposition by Givens Rotations. We present FPGA implementations of borh orchitectures und compare them with un ASIC-bused solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost ure not critical.

Original language	English
Title of host publication	Unknown Host Publication
Place of Publication	Online
Publisher	IEEE
Pages	1375-1380
Number of pages	6
ISBN (Print)	0-7803-5700-0
DOIs	https://doi.org/10.1109/ACSSC.1999.831931
Publication status	Published (in print/issue) - 6 Aug 2002
Event	Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999. - Pacific Grove, CA, USA , USA Duration: 6 Aug 2002 → …

Conference

Conference	Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999.
Period	6/08/02 → …

Bibliographical note

Reference text: [ I ] A. Farina, Antenna-Based Signal Processing Techniques for Radar Systems, Artech House, 1991.
[2] S. Haykin, Adaptive Filter Theory, 2nd Edition, Prentice Hall,
[3] W. M. Gentleman and H. T. Kung, “Matrix triangularization by systolic arrays”, Proc. SPIE 298, Real-Time Signal Processing N, pp. 19-26, 1981.
[4] C. M. Rader, “VLSI Systolic Arrays for Adaptive Nulling”, IEEE Sig. Proc. Mag, Vol. 13, No. 4, pp. 29-49, 1996.
[ 5 ] J. Volder, ‘The CORDIC Trigonometric Computing Technique”, IRE Trans. Electron. Comput., Vol. EC-8, pp. 330-334, 1959.
[6] G. Lightbody, R. L. Walke, R. Woods, J. McCanny, “Novel Mapping of a Linear QR Architecture”, Proc. ICASSP, vol. IV, pp.
[7] R. Dohler, “Squared Givens Rotations”, IMA J. of NumericalAnalysis, Vol. Il,pp. 1-5, 1991.
[8] S. Y. Kung, VLSIArruy Processors, Prentice Hall, ISBN 0-13-942749-X, 1988.
[9] G. M. Megson, An Introduction to Systolic Algorithm Design, Clarendon Press, ISBN 0-19-853813-8, 1992.

Keywords

QR-RLS
VLSI
VHDL
CORDIC
systolic arrays

Access to Document

10.1109/ACSSC.1999.831931

StampFinal published version, 290 bytes
ArchForAdaptWeighCalc WalkeFinal published version, 687 KB

Cite this

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abstract = "We compare two parallel urray architectures for adaptive weight calculation based on QR-decomposition by Givens Rotations. We present FPGA implementations of borh orchitectures und compare them with un ASIC-bused solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost ure not critical.",

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Architectures for adaptive weight calculation on ASIC and FPGA

Abstract

Conference

Bibliographical note

Keywords

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