Architecture for dual-mode quadruple precision floating point adder

Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a configurable dual-mode architecture for floating point (F.P.) adder. The architecture(named as QPdDP) works in dual-mode which can operates either for quadruple precision or dual (two-parallel) double precision. The architecture follows the standard state-of-the-art flow for floating point adder. It is aimed for the computation of normal as well as sub-normal operands, along with the support for the exceptional case handling. The key sub-components in the architecture are re-designed & optimized for on-the-fly dual-mode processing, which enables efficient resource sharing for dual precision operands. The data-path is optimized for minimal multiplexing circuitry overhead. The presented dual-mode architecture provide SIMD support for double precision operands, along with high (quadruple) precision support. The proposed architecture is synthesized using UMC 90nmtechnology ASIC implementation. It is compared with the best available literature works, and have shown better design metrics in terms of area, period and area × period, along with more computational support.
Original languageEnglish
Title of host publicationIEEE Computer Society Annual Symposium on VLSI
ISBN (Electronic)10.1109/ISVLSI.2015.70
DOIs
Publication statusPublished - 2015

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Jaiswal, M. K., Varma, B. S. C., & So, H. K-H. (2015). Architecture for dual-mode quadruple precision floating point adder. In IEEE Computer Society Annual Symposium on VLSI https://doi.org/10.1109/ISVLSI.2015.70